gtl2018 NXP Semiconductors, gtl2018 Datasheet

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gtl2018

Manufacturer Part Number
gtl2018
Description
Gtl2018 8-bit Lvttl To Gtl Transceiver
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
gtl2018PW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features
3. Quick reference data
Table 1.
Symbol
C
C
GTL; V
t
t
t
t
PLH
PHL
PLH
PHL
i
io
ref
= 0.8 V; V
Quick reference data
Parameter
input capacitance
input/output capacitance
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
TT
= 1.2 V
The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system
interface with a GTL /GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL
or 5 V CMOS inputs.
I
I
I
I
I
I
I
I
GTL2018
8-bit LVTTL to GTL transceiver
Rev. 01 — 15 February 2007
Operates as an octal GTL /GTL/GTL+ sampling receiver or as an LVTTL to
GTL /GTL/GTL+ driver
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
GTL input and output 3.6 V tolerant
V
Partial power-down permitted
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
Package offered: TSSOP24
ref
adjustable from 0.5 V to 0.5V
Conditions
control inputs;
V
A port; V
B port; V
An to Bn; see
An to Bn; see
Bn to An; see
Bn to An; see
I
= 3.0 V or 0 V
O
O
CC
= 3.0 V or 0 V
= V
TT
Figure 3
Figure 3
Figure 4
Figure 4
or 0 V
Min
-
-
-
-
-
-
-
Typ
2
4.6
3.4
2.8
3.4
5.2
4.9
Product data sheet
Max
2.5
6
4.3
5
7
8
7
Unit
pF
pF
pF
ns
ns
ns
ns

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gtl2018 Summary of contents

Page 1

... The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL /GTL/GTL+ bus. The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver LVTTL-to-GTL interface. The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL CMOS inputs. 2. Features I ...

Page 2

... NXP Semiconductors 4. Ordering information Table 2. Ordering information +85 C. amb Type number Topside mark GTL2018PW GTL2018PW 5. Functional diagram Fig 1. Logic diagram of GTL2018 GTL2018_1 Product data sheet Package Name Description TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm GTL2018 & B0 & ...

Page 3

... GTL reference voltage 13 direction control input (LVTTL) 14, 24 positive supply voltage 15 data inputs/outputs (A side, LVTTL Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver GND ...

Page 4

... A port 0.5 [1] B port 0.5 V < [1] output in OFF or 0.5 HIGH state; A port [1] output in OFF or 0.5 HIGH state; B port [2] A port - [2] B port - [3] A port - [4] 60 GTL2018 Max Unit 4 7 7 +150 C © NXP B.V. 2007. All rights reserved ...

Page 5

... B port HIGH-level output A port current LOW-level output B port current A port ambient temperature operating in free air maximum of 3.6 V with resistor sized 3 configured as outputs (DIR = LOW). I(max) Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver [1] Min Typ Max 3.0 - 3.6 0.85 0.9 0.95 1.14 1.2 1.26 1 ...

Page 6

... A port or control inputs 3 0 control inputs 3 port 3 port 3.3 V and amb Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver = +85 C. amb [1] Min Typ Max [ [2] 2 [2] - 0.23 0.4 [2] - 0.28 ...

Page 7

... An to Bn; see Figure An; see Figure An; see Figure amb 3 0. for B ports 3 002aab140 V = 1.5 V for A port and V for M ref B port Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver [1] Min Typ - 2.8 - 3.3 - 5.3 - 5.2 - 2.8 - 3.4 - 5.2 - 4.9 - 2.8 - 3.4 - 5 2.7 V for A ports and control pins; ...

Page 8

... V I PULSE GENERATOR PULSE GENERATOR R = load resistor load capacitance; includes jib and probe capacitance termination resistance; should be equal Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver ref PHL V OH 1 002aab142 2 ...

Page 9

... Rev. 01 — 15 February 2007 8-bit LVTTL to GTL transceiver detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION GTL2018 SOT355 ( 0.5 8 0.1 o 0.2 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2007. All rights reserved ...

Page 10

... Solder bath specifications, including temperature and impurities GTL2018_1 Product data sheet Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver © NXP B.V. 2007. All rights reserved ...

Page 11

... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 8. Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver Figure 8) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...

Page 12

... Gunning Transceiver Logic Human Body Model Low Voltage Transistor-Transistor Logic Machine Model Pulse Repetition Rate Transistor-Transistor Logic Data sheet status Product data sheet Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver peak temperature 001aac844 Change notice Supersedes - - © NXP B.V. 2007. All rights reserved. ...

Page 13

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 15 February 2007 GTL2018 8-bit LVTTL to GTL transceiver © NXP B.V. 2007. All rights reserved ...

Page 14

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com GTL2018 All rights reserved. Date of release: 15 February 2007 Document identifier: GTL2018_1 ...

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