gtl2107 NXP Semiconductors, gtl2107 Datasheet

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gtl2107

Manufacturer Part Number
gtl2107
Description
12-bit Gtl To Lvttl Translator With Power Good Control And High-impedance Lvttl And Gtl Outputs
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
3. Quick reference data
Table 1.
T
Symbol
C
V
t
t
V
t
t
PLH
PHL
PLH
PHL
amb
ref
ref
io
= 0.73 V; V
= 0.76 V; V
= 25 C
Parameter
input/output capacitance A port; V
LOW-to-HIGH
propagation delay
HIGH-to-LOW
propagation delay
LOW-to-HIGH
propagation delay
HIGH-to-LOW
propagation delay
Quick reference data
TT
TT
= 1.1 V
= 1.2 V
The GTL2107 is a customized translator between dual Xeon processors,
GTL /GTL/GTL+ I/O and the Platform Health Management, South Bridge and Power
Supply 3.3 V LVTTL and GTL signals.
I
I
I
I
I
I
I
I
I
GTL2107
12-bit GTL /GTL/GTL+ to LVTTL translator
Rev. 04 — 6 July 2007
Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
Operates at GTL, GTL+ or GTL levels
EN1 and EN2 enable control
3.0 V to 3.6 V operation
LVTTL I/O not 5 V tolerant
Series termination on the LVTTL outputs of 30
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds
500 mA
Package offered: TSSOP28
Conditions
B port; V
nA to nBI; see
nBI to nA or nAO (open-drain outputs); see
nA to nBI; see
nBI to nA or nAO (open-drain outputs); see
nA to nBI; see
nBI to nA or nAO (open-drain outputs); see
nA to nBI; see
nBI to nA or nAO (open-drain outputs); see
O
O
= 3.0 V or 0 V
= V
TT
Figure 4
Figure 4
Figure 4
Figure 4
or 0 V
Figure 14
Figure 14
Figure 14
Figure 14
Min
-
-
1
2
2
2
1
2
2
2
Product data sheet
Typ
3.0
2.0
4
13
5.5
4
4
13
5.5
4
Max Unit
4.0
3.0
8
18
10
10
8
18
10
10
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns

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gtl2107 Summary of contents

Page 1

... GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator Rev. 04 — 6 July 2007 1. General description The GTL2107 is a customized translator between dual Xeon processors, GTL /GTL/GTL+ I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL and GTL signals. 2. Features I Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver ...

Page 2

... The enable on 7BO1/7BO2 include a delay that prevents the transient condition (where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns) from causing a LOW glitch on the 7BO1/7BO2 outputs. Fig 1. Logic diagram of GTL2107 GTL2107_4 Product data sheet Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm DELAY Rev. 04 — ...

Page 3

... V) 15 data output (LVTTL), push-pull 16 data output (GTL) 17 data output (GTL) 18 data input (GTL) 19 data input (GTL) Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator 1BI 26 2BI 25 7BO1 24 7BO2 23 EN2 22 ...

Page 4

... Power supervisor power good control Output 3BI/4BI 3AO/4AO (open-drain Southbridge SMI_L control Output 9AO (push-pull Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator © NXP B.V. 2007. All rights reserved ...

Page 5

... [ [ Southbridge NMI control Input/output 11A (open-drain Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator Output 7BO1/7BO2 [ Output 11BO © NXP B.V. 2007. All rights reserved ...

Page 6

... GTL2107 11A 5BI 9BI 6BI 3AO 3BI 4AO 4BI 10AI1 10BO1 10AI2 10BO2 GND 9AO Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator 56 V CPU1 IERR_L THRMTRIP L FORCEPR_L PROCHOT L NMI CPU1 SMI L FORCEPR_L PROCHOT L IERR_L THRMTRIP L NMI CPU2 SMI L CPU2 © ...

Page 7

... OFF or HIGH state; B port [2] A port B port [3] A port Conditions GTL GTL GTL+ overall GTL GTL GTL+ A port B port A port and ENn B port A port and ENn B port A port Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator Min Max 0.5 +4.6 - [1] 0.5 +4.6 [1] 0.5 +4.6 - [1] 0.5 +4.6 [1] 0.5 +4 ...

Page 8

... A port or control inputs 3 0 port 3 port 3.3 V and amb Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator Min Typ Max - - + +85 C amb [1] Min Typ [2] V ...

Page 9

... Figure 8 EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 EN1 to nAO or EN2 to nAO; see Figure 8 EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 EN2 to 9AO; see Figure 11 EN2 to 9AO; see Figure 11 Rev. 04 — 6 July 2007 GTL2107 [1] Min Typ Max Unit 5 ...

Page 10

... EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 EN1 to nAO or EN2 to nAO; see Figure 8 EN1 to 5A (I/O) or EN2 to 6A (I/O); see Figure 8 EN2 to 9AO; see Figure 11 EN2 to 9AO; see Figure amb Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator [1] Min Typ 5 ...

Page 11

... PLH PHL output V ref A port to B port input V V ref ref t t PZL PLZ output 1.5 V input 1 PLZ PZL output EN2 to nAO GTL2107 3 ref V OL 002aab000 0 002aab002 3 1 ...

Page 12

... V OH output 1 002aac196 Fig 10. 11A to 11BO input 1 PHZ PZH output Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator input 1 PLH PHL V ref 002aac197 3 1 002aab980 © NXP B.V. 2007. All rights reserved. ...

Page 13

... V I PULSE DUT GENERATOR PULSE DUT GENERATOR PULSE DUT GENERATOR pulse generators. o Rev. 04 — 6 July 2007 GTL2107 500 50 pF 002aab981 002aab264 1 002aab265 ...

Page 14

... Rev. 04 — 6 July 2007 12-bit GTL /GTL/GTL+ to LVTTL translator detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION GTL2107 SOT361 ( 0.8 8 0.1 o 0.5 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2007. All rights reserved ...

Page 15

... Solder bath specifications, including temperature and impurities GTL2107_4 Product data sheet 12-bit GTL /GTL/GTL+ to LVTTL translator Rev. 04 — 6 July 2007 GTL2107 © NXP B.V. 2007. All rights reserved ...

Page 16

... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 17. Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator Figure 17) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...

Page 17

... Gunning Transceiver Logic Human Body Model Low Voltage Transistor-Transistor Logic Machine Model Pulse Rate Repetition Transistor-Transistor Logic Voltage Regulator Down Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator peak temperature 001aac844 © NXP B.V. 2007. All rights reserved. time ...

Page 18

... B port: Max value changed from 2 3 Objective data sheet Product data sheet Product data sheet Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator Change notice Supersedes - GTL2107_3 characteristics”: - GTL2008_GTL2107_2 - GTL2008_1 - - © NXP B.V. 2007. All rights reserved ...

Page 19

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 04 — 6 July 2007 GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator © NXP B.V. 2007. All rights reserved ...

Page 20

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com GTL2107 All rights reserved. Date of release: 6 July 2007 Document identifier: GTL2107_4 ...

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