pdi1394p11a NXP Semiconductors, pdi1394p11a Datasheet
pdi1394p11a
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pdi1394p11a Summary of contents
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... PDI1394P11A 3-port physical layer interface Preliminary specification Philips Semiconductors INTEGRATED CIRCUITS 1999 Mar 10 ...
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... The Link Layer Controller interface is compatible with both 3V and 5V Link Controllers. While providing a maximum transmission data rate of 200 Mb/s, the PDI1394P11A is compatible with current 100 Mb/s Physical Layer ICs. The PDI1394P11A is available in the LQFP64 package. OUTSIDE NORTH AMERICA NORTH AMERICA PDI1394P11A BD ...
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... Cable termination voltage supplies – PLL circuit ground I/O PLL external filter capacitor I Crystal oscillator connection O Crystal oscillator connection – PLL circuit power – External current setting resistor I* Link interface isolation status input 3 Preliminary specification PDI1394P11A supply when a 5V LLC is connected to the ...
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... The PDI1394P11A receives data to be transmitted over the bus from two or four parallel data paths to the Link Controller, D[0:3]. These data paths are latched and synchronized with the 49.152 MHz clock. ...
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... Mar 10 presence of the remotely supplied twisted-pair bias voltage, indicating the cable connection status. The PDI1394P11A provides a nominal 1.85 V for driver load termination. This bias voltage, when seen through a cable by a remote receiver, is used to sense the presence of an active connection. The value of this bias voltage has been chosen to allow inter-operability between transceiver chips operating from either 5 V nominal supplies ...
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... W load Driver enabled, speed signaling OFF 200Mbit speed signaling enabled Drivers disabled TEST CONDITION TEST CONDITION Driver disabled Driver disabled Driver disabled Driver disabled Driver disabled Driver disabled 6 Preliminary specification PDI1394P11A LIMITS UNIT UNIT MIN MAX –0.3 4.6 V –0 –0.5 5 ...
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... ISO– 1 high ISO– = high 0 TEST CONDITION TEST CONDITION Board mounted, no air flow 7 Preliminary specification PDI1394P11A LIMITS UNIT UNIT MIN TYP MAX 60 mA 175 mA 1 4.7 7.5 V – 0.55 V 0.5 V 1.0 A 5.0 A –20 – ...
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... L 90 50% to 50% See Figure 1 50% to 50% See Figure 1 50% to 50% See Figure 2 SYSCLK 50% Dn, CTLn SV00238 Figure 2. Dn, CTLn, output delay relative to SYSCLK 8 Preliminary specification PDI1394P11A LIMITS UNIT UNIT MIN TYP MAX 0.25 ns 0.15 ns 2 ...
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... Rd/Wr Cable Power Status is also included in this register to expedite handling the CPSint Rd/Wr Indicates that the last bus reset was initiated in the PDI1394P11A. This bit is also included in the self ID packet set, this node is a contender for the role of bus or Isochronous Resource Manager. ...
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... V DD LINK LAYER CONTROLLER INTERFACE Figure 3. External Component Connections 400K CPS 1 F TPBIAS 56 56 TPAn+ TPAn– TPBn+ TPBn– 250pF 5K 10 Preliminary specification PDI1394P11A AGND 32 CNA CNA OUT 31 PC0 30 POWER-CLASS PC1 29 PROGRAMMING PC2 28 CONTENDER C/LKON 10K 27 PROGRAMMING AGND 26 AVDD ...
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... CPSint bit. However, if the CPS input is still low, another cable-power status interrupt immediately occurs. The cable voltage at which these events occur is adjustable on the PDI1394P11A. 1999 Mar 10 PDI1394P11A The external resistor (R) needed to set the CPS trip voltage ( desired voltage can be calculated using the following equation ...
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... Bushold and Link/PHY single capacitor galvanic isolation 17.3.1 Bushold The PDI1394P11A uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by a 3-Stated device or input coupling capacitor. Unterminated high impedance inputs react to ambient electrical noise which cause internal oscillation and excess power supply current draw ...
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... Test Mode control and ISBR mode inputs (TESTM[1:2], pins[22,21]) These two logic signals are used in manufacturing to enable production line testing of the PDI1394P11A. For normal use these should be tied enable ISBR (Arbitrated (short) bus reset) DD mode, set TESTM1 high and TESTM2 low. See section 17.1 for more information on ISBR mode ...
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... In addition there are two bi-directional control lines CTL[0:1], the 50 MHz SYSCLK line from the phy to the link, and the link request line LREQ from the link to the phy. The PDI1394P11A has control of all the bi-directional pins. The link is allowed to drive these pins only after it has been given permission by the phy ...
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... The only defined condition when the phy automatically sends a register to the link is after self-ID, when it sends the physical-ID register which contains the new node address. The definition of the bits in the status transfer are shown below. 15 Preliminary specification PDI1394P11A LR(n–2) LR(n–1) SV00232 ...
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... These bits hold the address of the phy register whose contents will be transferred to the link. 8–15 Data The data that sent to the link. 21.0 STATUS TRANSFER TIMING PHY 00 01 CTL [0:1] PHY 00 S[0,1] D [0:1] 1999 Mar S[2,3] S[14,15] Figure 9. Status Transfer Timing 16 Preliminary specification PDI1394P11A SV00233 ...
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... This causes their Phys to see a header CRC error and the packet to be discarded. The PDI1394P11A compensates for this by extending the Data_Prefix time before sending the packet. This makes the PDI1394P11A fully compatible with all existing 100 Mbps Phys on the market. ZZ ...
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... Node may be powered from the bus, and is using additional needed to enable the LLC and higher layers. 1999 Mar 1111 SPD Figure 11. Receive Timing Waveforms DESCRIPTION 18 Preliminary specification PDI1394P11A 0000 0000 n SV00234 ...
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... Philips Semiconductors 3-port physical layer interface LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm 1999 Mar 10 PDI1394P11A 19 Preliminary specification SOT314-2 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors 1999 Mar 10 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 20 Preliminary specification PDI1394P11A All rights reserved. Printed in U.S.A. Date of release: 03-99 9397 750 05499 ...