pdi1394p11 NXP Semiconductors, pdi1394p11 Datasheet
pdi1394p11
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pdi1394p11 Summary of contents
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... PDI1394P11 3-port physical layer interface Product specification Supersedes data of 1998 Sep 24 Philips Semiconductors INTEGRATED CIRCUITS 1999 Apr 09 ...
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... The Link Layer Controller interface is compatible with both 3V and 5V Link Controllers. While providing a maximum transmission data rate of 200 Mb/s, the PDI1394P11 is compatible with current 100 Mb/s Physical Layer ICs. The PDI1394P11 is available in the LQFP64 package. OUTSIDE NORTH AMERICA ...
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... Cable termination voltage supplies – PLL circuit ground I/O PLL external filter capacitor I Crystal oscillator connection O Crystal oscillator connection – PLL circuit power – External current setting resistor I* Link interface isolation status input 3 Product specification PDI1394P11 supply when a 5V LLC is connected to the ...
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... The PDI1394P11 receives data to be transmitted over the bus from two or four parallel data paths to the Link Controller, D[0:3]. These data paths are latched and synchronized with the 49.152 MHz clock. ...
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... Apr 09 presence of the remotely supplied twisted-pair bias voltage, indicating the cable connection status. The PDI1394P11 provides a nominal 1.85 V for driver load termination. This bias voltage, when seen through a cable by a remote receiver, is used to sense the presence of an active connection. The value of this bias voltage has been chosen to allow inter-operability between transceiver chips operating from either 5 V nominal supplies ...
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... W load Driver enabled, speed signaling OFF 200Mbit speed signaling enabled Drivers disabled TEST CONDITION TEST CONDITION Driver disabled Driver disabled Driver disabled Driver disabled Driver disabled Driver disabled 6 Product specification PDI1394P11 LIMITS UNIT UNIT MIN MAX –0.3 4.6 V –0 –0.5 5 ...
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... ISO– 1 high ISO– = high 0 TEST CONDITION TEST CONDITION Board mounted, no air flow 7 Product specification PDI1394P11 LIMITS UNIT UNIT MIN TYP MAX 60 mA 175 mA 1 4.7 7.5 V – 0.55 V 0.5 V 1.0 A 5.0 A –20 – ...
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... L 90 50% to 50% See Figure 1 50% to 50% See Figure 1 50% to 50% See Figure 2 SYSCLK 50% Dn, CTLn SV00238 Figure 2. Dn, CTLn, output delay relative to SYSCLK 8 Product specification PDI1394P11 LIMITS UNIT UNIT MIN TYP MAX 0.25 ns 0.15 ns 2 ...
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... Rd/Wr Cable Power Status is also included in this register to expedite handling the CPSint Rd/Wr Indicates that the last bus reset was initiated in the PDI1394P11. This bit is also included in the self ID packet set, this node is a contender for the role of bus or Isochronous Resource Manager. ...
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... V DD LINK LAYER CONTROLLER INTERFACE Figure 3. External Component Connections 400K CPS 1 F TPBIAS 56 56 TPAn+ TPAn– TPBn+ TPBn– 250pF 5K 10 Product specification PDI1394P11 AGND 32 CNA CNA OUT 31 PC0 30 POWER-CLASS PC1 29 PROGRAMMING PC2 28 CONTENDER C/LKON 10K 27 PROGRAMMING AGND 26 AVDD ...
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... CPSint bit. However, if the CPS input is still low, another cable-power status interrupt immediately occurs. The cable voltage at which these events occur is adjustable on the PDI1394P11. 1999 Apr 09 The external resistor (R) needed to set the CPS trip voltage ( desired voltage can be calculated using the following equation ...
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... This pin supports an optional isolation barrier. 18.6 Control I/Os (CTL[0:1], pins[11,12]) These are bi-directional signals used in the communication between the PDI1394P11 and the link layer controller that control passage of information between the two devices. These pins support an optional isolation barrier. 18.7 Data I/Os (D[0:3], pins [13,14,15,16]) ...
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... In addition there are two bi-directional control lines CTL[0:1], the 50 MHz SYSCLK line from the phy to the link, and the link request line LREQ from the link to the phy. The PDI1394P11 has control of all the bi-directional pins. The link is allowed to drive these pins only after it has been given permission by the phy ...
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... The only defined condition when the phy automatically sends a register to the link is after self-ID, when it sends the physical-ID register which contains the new node address. The definition of the bits in the status transfer are shown below. 14 Product specification PDI1394P11 LR(n–2) LR(n–1) SV00232 ...
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... These bits hold the address of the phy register whose contents will be transferred to the link. 8–15 Data The data that sent to the link. 21.0 STATUS TRANSFER TIMING PHY 00 01 CTL [0:1] PHY 00 S[0,1] D [0:1] 1999 Apr S[2,3] S[14,15] Figure 7. Status Transfer Timing 15 Product specification PDI1394P11 SV00233 ...
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... 0000 0000 0000 0000 ZZZZ ZZZZ ZZZZ ZZZZ Figure 8. Transmit Timing Waveforms 16 Product specification PDI1394P11 ZZZZ ZZZZ ZZZZ 0000 0000 0000 ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ 01 01 ...
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... Node may be powered from the bus, and is using additional needed to enable the LLC and higher layers. 1999 Apr 1111 SPD Figure 9. Receive Timing Waveforms DESCRIPTION 17 Product specification PDI1394P11 0000 0000 n SV00234 ...
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... Philips Semiconductors 3-port physical layer interface LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm 1999 Apr 09 18 Product specification PDI1394P11 SOT314-2 ...
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... Philips Semiconductors 3-port physical layer interface 1999 Apr 09 NOTES 19 Product specification PDI1394P11 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors 1999 Apr 09 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 20 Product specification PDI1394P11 All rights reserved. Printed in U.S.A. Date of release: 04-99 9397 750 05511 ...