pdi1394p21 NXP Semiconductors, pdi1394p21 Datasheet - Page 28

• Manufacturer Part Number: pdi1394p21
• Description: 3-port Physical Layer Interface
• Manufacturer: NXP Semiconductors

the data-prefix state on the serial bus followed by the data-end state,
whenever the LLC immediately releases the bus without transmitting
Philips Semiconductors
18.3 Receive
Whenever the PHY detects the data-prefix state on the serial bus, it
initiates a receive operation by asserting Receive on the CTL terminals
and a logic 1 on each of the D terminals (“data-on” indication). The
PHY indicates the start of a packet by placing the speed code
(encoded as shown in Table 19) on the D terminals, followed by
packet data. The PHY holds the CTL terminals in the Receive state
until the last symbol of the packet has been transferred. The PHY
indicates the end of packet data by asserting Idle on the CTL
terminals. All received packets are transferred to the LLC. Note that
the speed code is part of the PHY-LLC protocol and is not included in
the calculation of CRC or any other data protection mechanisms.
Table 19. Speed Code for the Receiver
It is possible for the PHY to receive a null packet, which consists of
without any packet data. A null packet is transmitted whenever the
packet speed exceeds the capability of the receiving PHY, or
any data. In this case, the PHY will assert Receive on the CTL
terminals with the “data-on” indication (all 1’s) on the D terminals,
followed by Idle on the CTL terminals, without any speed code or
data being transferred. In all cases, in normal operation, the
NOTE: SPD = Speed code; see Table 19; d0–dn = Packet data.
2001 Sep 06
D0–D7
0000 0000
0100 0000
0101 0000
1111 1111
3-port 400 Mbps physical layer interface
CTL0, CTL1
SYSCLK
D0–D7
00
01
XX
DATA RATE
S100
S200
S400
“data-on” indication
FF (“data-on”)
(b)
Figure 16. Normal Packet Reception Timing
(a)
28
10
SPD
(c)
PDI1394P21 sends at least one “data-on” indication before sending
the speed code or terminating the receive operation.
The PDI1394P21 also transfers its own self-ID packet, transmitted
during the self-ID phase of bus initialization to the LLC. This packet
is transferred to the LLC just as any other received self-ID packet.
The sequence of events for a normal packet reception is as follows:
Receive operation initiated. The PHY indicates a receive
operation by asserting Receive on the CTL lines. Normally, the
interface is idle when receive is asserted. However, the receive
operation may interrupt a status transfer operation that is in
progress so that the CTL lines may change from status to receive
without an intervening idle.
Data-on indication. The PHY may assert the data-on indication code
on the D lines for one or more cycles preceding the speed code.
Speed code. the PHY indicates the speed of the received packet
by asserting a speed code on the D lines for one cycle
immediately preceding packet data. The link decodes the speed
code on the first Receive cycle for which the D lines are not the
data-on code. If the speed code is invalid, or indicates a speed
higher than that which the link is capable of handling, the link
should ignore the subsequent data.
Receive data. Following the data-on indication (if any) and the
speed code, the PHY asserts packet data on the D lines with
receive on the CTL lines for the remainder of the receive operation.
Receive operation terminated. The PHY terminates the receive
operation by asserting the idle on the CTL lines. The PHY asserts
at least one cycle of idle following a receive operation.
(d)
d0
dn
PDI1394P21
SV01760
00
(e)
00
Preliminary data