pdi1394p22 NXP Semiconductors, pdi1394p22 Datasheet
pdi1394p22
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pdi1394p22 Summary of contents
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... PDI1394P22 3-port physical layer interface Objective specification hilips Semiconductors INTEGRATED CIRCUITS 1999 Jul 09 ...
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... The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PDI1394P22 is designed to interface with a Link Layer Controller (LLC), such as the PDI1394L11 or PDI1394L21. OUTSIDE NORTH AMERICA ...
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... Cable Power Status input. This terminal is normally connected to cable power through a 370–410 k resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. I/O Control I/Os. These bi-directional signals control communication between the PDI1394P22 and the LLC. Bus holders are built into these terminals. 3 Objective specification PDI1394P22 ...
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... I/O Data I/Os. These are bi-directional data signals between the PDI1394P22 and the LLC. Bus holders are built into these terminals. — Digital circuit power terminals. A combination of high frequency decoupling capacitors near each terminal are suggested, such as paralleled 0 ...
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... LLC. I Test control input. This input is used in manufacturing tests of the PDI1394P22. For normal use, this terminal should be tied to GND. I Test control input. This input is used in manufacturing tests of the PDI1394P22. For normal use, this terminal should be tied to GND. ...
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... TPBIAS2 PD /RESET 7.0 FUNCTIONAL SPECIFICATION The PDI1394P22 requires only an external 24.576 MHz crystal as a reference. An external clock can be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded Strobe and Data information ...
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... TPBIAS voltage on the other end of the cable. When the PDI1394P22 is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB– ...
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... Between TPA and TPB cable inputs, S00 operation Between TPA and TPB cable inputs, S200 operation Between TPA and TPB cable inputs, S400 operation Crystal connected according to Figure 8 or external clock input at pin XI 8 Objective specification PDI1394P22 LIMITS UNIT UNIT MIN MAX –0.5 4 ...
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... Drivers disabled –30 Drivers disabled 0.6 Drivers disabled 89 Drivers disabled –168 TPBIAS–TPA common mode 49 voltage, drivers disabled TPBIAS–TPA common mode 314 voltage, drivers disabled Drivers disabled 9 Objective specification PDI1394P22 LIMITS UNIT UNIT TYP MAX 265 0.88 mA –0.44 mA –2.53 mA –8.10 ...
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... 0. LREF DD /ISO = 0. LREF DD At rated I current the maximum current is tbf Objective specification PDI1394P22 MIN TYP MAX UNIT tbf mA tbf mA tbf mA tbf mA tbf tbf mA 7.5 8.0 8.5 V 2 – ...
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... At 1394 connector 90% to 10%; At 1394 connector 50% to 50%; See Figure 2 50% to 50%; See Figure 2 50% to 50%; See Figure 3 SYSCLK Dn, CTLn, LREQ Figure 3. Dn, CTLn, output delay relative to SYSCLK SV01099 11 Objective specification PDI1394P22 LIMITS UNIT UNIT MIN TYP MAX TBD C/W MIN TYP ...
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... Extended register definition. For the PDI1394P22, this field is 111b, indicating that the extended register set is implemented. Num_Ports 4 Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the PDI1394P22 this field is 3. PHY_Speed 3 Rd PHY speed capability. For the PDI1394P22, this field is 010b, indicating S400 speed capability. ...
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... Port_Select 4 Rd/Wr Port_Select. This field selects the port when accessing per-port status or control (e.g., when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset hardware reset and is unaffected by bus reset. 1999 Jul 09 DESCRIPTION 13 Objective specification PDI1394P22 ...
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... Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the selected port, encoded as follows: The Peer_Speed field is invalid after a bus reset until self-ID has completed. NOTE: Peer speed codes higher than 010b (S400) are defined in P1394a. However, the PDI1394P22 is only capable of detecting peer speeds up to S400. PIE ...
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... Manufacturer’s organizationally unique identifier (OUI). For the PDI1394P22, this field is 00_06_37h (Philips Semiconductors) (the MSB is at register address 1010b). Product_ID 24 Rd Product identifier. For the PDI1394P22, this field is 43_11_00h (the MSB is at register address 1101b). 1999 Jul 09 BIT POSITION ...
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... PAIR B TPBn– 220pF 5 k OUTER CABLE SHIELD 1 M 0.01 F 0.001 F Figure 5. Typical outer shield termination LINK POWER SQUARE WAVE INPUT SV01781 Figure 7. Non-isolated connection variations for LPS 16 Objective specification PDI1394P22 OUTER SHIELD TERMINATION SV01744 SV01748 1 k LPS LPS 1 k SV01750 ...
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... PDI1394P22 370– 410 k Figure 8. External Component Connections 17 Objective specification PDI1394P22 50 49 0.3–1.0 F TPBIAS2 48 TPBIAS TPA2+ 47 TPA2– CABLES INTERFACE TPB2+ 45 CONNECTION TPB2– 44 0.3–1.0 F AVDD 43 TPBIAS1 42 TPBIAS TPA1 CABLES TPA1– ...
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... P1394a PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The PDI1394P22 correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover 7-bit bus request is immediately followed by another request (e ...
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... Philips Semiconductors 3-port physical layer interface 18.0 PRINCIPLES OF OPERATION The PDI1394P22 is designed to operate with an LLC such as the Philips Semiconductors PDI1394L11 or PDI1394L21. The following paragraphs describe the operation of the PHY-LLC interface. The interface to the LLC consists of the SYSCLK, CTL0–CTL1, D0–D7, LREQ, LPS, C/LKON, and /ISO terminals on the PDI1394P22 as shown in Figure 9 ...
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... All others NOTE: The PDI1394P22 will accept a bus request with an invalid speed code and process the bus request normally. However, during packet transmission for such a request, the PDI1394P22 will ignore any data presented by the LLC and will transmit a null packet. ...
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... The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the PDI1394P22 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start packet is imminent, and then re-enables the enhancements when it receives a cycle start packet ...
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... Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines bus reset is pending, the PHY may also assert Grant on the CTL line immediately following a complete status transfer. DESCRIPTION ( S[0:1] S[14:15] Figure 11. Status Transfer Timing 22 Objective specification PDI1394P22 ( SV01759 ...
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... FF (“data-on”) NOTE: SPD = Speed code; see Table 17; d0–dn = Packet data. 1999 Jul 09 PDI1394P22 sends at least one “data-on” indication before sending the speed code or terminating the receive operation. The PDI1394P22 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization to the LLC. This packet is transferred to the LLC just as any other received self-ID packet ...
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... D lines for one or more cycles. Receive operation terminated. The PHY terminates the receive operation by asserting Idle on the CTL lines. The PHY shall assert at least one cycle of Idle following a receive operation. (a) 10 (b) FF (“data-on”) Figure 13. Null Packet Reception Timing 24 Objective specification PDI1394P22 00 (c) 00 SV01761 ...
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... Link Controls Ctl and D PHY High-impedance Ctl and D Outputs Figure 14. Normal Packet Transmission Timing 25 Objective specification PDI1394P22 ( SPD ...
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... After regaining control of the interface, the PHY shall assert at least one cycle of Idle before any subsequent status transfer, receive operation, or transmit operation. (b) ( Link Controls Ctl and D PHY High-impedance Ctl and D Outputs Figure 15. Cancelled/Null Packet Transmission DESCRIPTION 26 Objective specification PDI1394P22 (d) ( SV01763 ...
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... Philips Semiconductors 3-port physical layer interface LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm 1999 Jul 09 27 Objective specification PDI1394P22 SOT314-2 ...
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... Philips Semiconductors 3-port physical layer interface LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm 1999 Jul 09 28 Objective specification PDI1394P22 SOT414-1 ...
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... Philips Semiconductors 3-port physical layer interface 1999 Jul 09 NOTES 29 Objective specification PDI1394P22 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 1999 Jul 09 [1] © Copyright Philips Electronics North America Corporation 1999 Document order number: 30 Objective specification PDI1394P22 All rights reserved. Printed in U.S.A. Date of release: 08-99 9397-750-06383 ...