w83977ctf Winbond Electronics Corp America, w83977ctf Datasheet - Page 64

• Manufacturer Part Number: w83977ctf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

4.2.3 Bank0.Reg2 - Interrupt Status Register (ISR)
Power on default <7:0> = 00000000 binary
7-3
Bit
2
1
0
Reserved
TMR_I
LSR_I
RXTH_I
Name
Read/Write
Read Only
Read Only
Read Only
-
Reserved
Timer Interrupt. Set to 1 when timer count to 0. This bit
will be affected by (1) the timer registers are defined in
Bank4.Reg0 and Bank1.Reg0~1, (2) EN_TMR(Enable
Timer, in Bank0.Reg3.Bit2) should be set to 1, (3)
ENTMR_I (Enable Timer Interrupt, in Bank0.Reg1.Bit2)
should be set to 1.
Line-Status-Register interrupt. Set to 1 when overrun,
or time out, or RBR Ready in the Line Status Register
(LSR) sets to 1. Clear to 0 when LSR is read.
Receiver Thershold-Level Interrupt. Set to 1 when (1)
the Receiver Buffer Register (RBR) is equal or larger
than the threshold level, (2) RBR occurs time-out if the
receiver buffer register has valid data and below the
threshold level. Clear to 0 when RBR is less than
threshold level from reading RBR.
-55 -
Publication Release Date: March 1999
Description
W83977EF/ CTF
PRELIMINARY
Revision A1