sta559bw STMicroelectronics, sta559bw Datasheet - Page 27

• Manufacturer Part Number: sta559bw
• Description: 5-volt, 2-amp, 2.1-channel High-efficiency Digital Audio System Sound Terminal
• Manufacturer: STMicroelectronics

STA559BW
6.1.3
To make the STA559BW work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock. It means that:
If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the
STA559BW immediately mutes the I
it freezes any active processing task.
Clock desyncronization can happen during STA559BW operation because of source
switching or TV channel change. To avoid audio side effects, like click or pop noise, it is
strongly recommended to complete the following actions:
1.
2.
while the serial audio interface and the internal PLL are still synchronous.
Delay serial clock enable
Table 20.
Channel input mapping
Table 21.
Each channel received via I
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers maps each I
Configuration register C (addr 0x02)
FFX power output mode
The FFX power output mode selects how the FFX output timing is configured.
Different power devices use different output modes.
5
6
7
Bit
Bit
N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles,
where N depends on the settings in
the PLL must be locked.
OCRB
D7
soft volume change
I
1
2
C read /write instructions
R/W
R/W
R/W
R/W
R/W
Delay serial clock enable
Channel input mapping
Reserved
D6
0
0
0
1
RST
RST
DSCKE
C1IM
C2IM
CSZ3
D5
2
0
S can be mapped to any internal processing channel via the
Doc ID 18190 Rev 1
2
Name
Name
S input channel to its corresponding processing channel.
2
S PCM data out (provided to the processing block) and
CSZ2
D4
Table 12 on page
1
0: processing channel 1 receives left I
1: processing channel 1 receives right I
0: processing channel 2 receives left I
1: processing channel 2 receives right I
0: no serial clock delay
1: serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
CSZ1
D3
0
23.
CSZ0
Description
Description
D2
2
1
S master devices
Register description
OM1
D1
1
2
2
S Input
S Input
2
2
S Input
S Input
OM0
D0
1
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