74abth16821adl NXP Semiconductors, 74abth16821adl Datasheet - Page 2

• Manufacturer Part Number: 74abth16821adl
• Description: 20-bit Bus-interface D-type Flip-flop; Positive-edge Trigger 3-state
• Manufacturer: NXP Semiconductors

FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN DESCRIPTION
Philips Semiconductors
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
1998 Feb 27
20-bit positive-edge triggered register
Multiple V
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
74ABTH16821A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Output capability: +64mA/-32mA
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
SYMBOL
C
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
I
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
t
t
I
C
PLH
PHL
CCZ
CCL
OUT
IN
CC
PACKAGES
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
4, 11, 18, 25, 32, 39, 46, 53
and GND pins minimize switching noise
PIN NUMBER
7, 22, 35, 50
56, 29
1, 28
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Quiescent supply current
Quiescent supply current
PARAMETER
TEMPERATURE RANGE
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
1Q0 - 1Q9
2Q0 - 2Q9
1OE, 2OE
1D0 - 1D9
2D0 - 2D9
SYMBOL
1CP, 2CP
GND
V
CC
OUTSIDE NORTH AMERICA
2
74ABTH16821A DGG
74ABT16821A DGG
74ABTH16821A DL
74ABT16821A DL
DESCRIPTION
The 74ABT16821A high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16821A has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active Low Output Enable (nOE) controls all ten 3-State buffers
independent of the register operation. When nOE is Low, the data in
the register appears at the outputs. When nOE is High, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
Two options are available, 74ABT16821A which does not have the
bus-hold feature and 74ABTH16821A which incorporates the
bus-hold feature.
Outputs disabled; V
Outputs LOW; V
T
V
amb
C
O
L
= 0V or V
= 50pF; V
V
CONDITIONS
= 25 C; GND = 0V
I
Data inputs
Data outputs
Output enable inputs (active-Low)
Clock pulse inputs (active rising edge)
Ground (0V)
Positive supply voltage
= 0V or V
CC
CC
CC
; 3-State
CC
CC
= 5V
= 5.5V
= 5.5V
NORTH AMERICA
BH16821A DGG
BT16821A DGG
BH16821A DL
BT16821A DL
FUNCTION
74ABTH16821A
74ABT16821A
TYPICAL
Product specification
500
2.4
2.0
10
3
7
DWG NUMBER
853-1796 19026
SOT371-1
SOT364-1
SOT371-1
SOT364-1
UNIT
mA
pF
pF
ns
A