n74f395n NXP Semiconductors, n74f395n Datasheet
n74f395n
Manufacturer Part Number
n74f395n
Description
4-bit Cascadable Shift Register 3-state
Manufacturer
NXP Semiconductors
Datasheet
1.N74F395N.pdf
(7 pages)
Philips Semiconductors
FEATURES
DESCRIPTION
The 74F395 is a 4-bit Shift Register with serial and parallel
synchronous operating modes and 3-State buffer outputs. The
shifting and loading operations are controlled by the state of the
Parallel Enable (PE) input. When PE is High, data is loaded from the
Parallel Data inputs (D0–D3) into the register synchronous with the
High-to-Low transition of the Clock input (CP). When PE is Low, the
data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and
the data in the register is shifted one bit to the right in the direction
(Q0!Q1!Q2!Q3) synchronous with the negative clock transition.
The PE and Data inputs are fully edge-triggered and must be stable
one setup prior to the High-to-Low transition of the clock.
The Master Reset (MR) is an asynchronous active-Low input. When
Low, the MR overrides the clock and all other inputs and clears the
register.
The 3-state output buffers are designed to drive heavily loaded
3-State buses, or large capacitive loads.
The active-Low Output Enable (OE) controls all four 3-State buffers
independent of the register operation. The data in the register
appears at the outputs when OE is Low. The outputs are in High
impedance “OFF” state, which means they will neither drive nor load
the bus when OE is High. The output from the last stage is brought
out separately. This output (Qs) is tied to the Serial Data input (Ds)
of the next register for serial expansion applications. The Qs output
is not affected by the 3-State buffer operation.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE:
One (1.0) FAST unit load is defined as: 20 A in the High state and 0.6mA in the Low state.
1990 Oct 23
4-bit parallel load shift register
Independent 3-State buffer outputs, Q0–Q3
Separate Qs output for serial expansion
Asynchronous Master Reset
4-bit cascadable shift register (3-State)
D0 – D3
Q0–Q3
PINS
MR
PE
OE
CP
Ds
Qs
Data inputs
Serial data input
Parallel Enable input
Master Reset input (active Low)
Output Enable input (active Low)
Clock Pulse input (active falling edge)
Serial expansion output
Data outputs (3-State)
DESCRIPTION
1
PIN CONFIGURATION
ORDERING INFORMATION
74F395
TYPE
16-pin plastic DIP
16-pin plastic SO
DESCRIPTION
TYPICAL f
120MHz
GND
MR
HIGH/LOW
74F (U.L.)
D0
D2
D3
PE
Ds
D1
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
50/33
1
2
3
4
5
6
7
8
MAX
V
CC
= 5V 10%, T
TYPICAL SUPPLY CURRENT
COMMERCIAL RANGE
16
15
14
13
12
10
11
9
N74F395N
N74F395D
V
Q0
Q1
Q2
Q3
Qs
CP
OE
Product specification
LOAD VALUE
(TOTAL)
CC
1.0mA/20mA
3.0mA/24mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
amb
32mA
HIGH/LOW
853–0370 00780
= 0 C to +70 C
74F395
SF00940
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n74f395n Summary of contents
Page 1
... GND SF00940 TYPICAL SUPPLY CURRENT MAX (TOTAL) 120MHz 32mA COMMERCIAL RANGE 10 + amb N74F395N N74F395D 74F (U.L.) LOAD VALUE HIGH/LOW HIGH/LOW 1.0/1.0 20 A/0.6mA 1.0/1.0 20 A/0.6mA 1.0/1.0 20 A/0.6mA 1.0/1.0 20 A/0.6mA 1.0/1.0 20 A/0.6mA 1.0/1.0 20 A/0.6mA 50/33 1.0mA/20mA 150/40 3.0mA/24mA 853–0370 00780 ...
Page 2
Philips Semiconductors 4-bit cascadable shift register (3-State) LOGIC SYMBOL Pin 16 ...
Page 3
Philips Semiconductors 4-bit cascadable shift register (3-State) MODE SELECT–FUNCTION TABLE INPUTS OUTPUTS ...
Page 4
Philips Semiconductors 4-bit cascadable shift register (3-State) DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL SYMBOL PARAMETER PARAMETER High-level output voltage High-level output voltage High-level output voltage Low-level ...
Page 5
Philips Semiconductors 4-bit cascadable shift register (3-State) AC ELECTRICAL CHARACTERISTICS SYMBOL SYMBOL PARAMETER PARAMETER f Maximum clock frequency MAX t Propagation delay PLH PHL t Propagation delay PLH PHL Propagation delay t ...
Page 6
Philips Semiconductors 4-bit cascadable shift register (3-State) AC WAVEFORMS For all waveforms 1.5V. M The shaded areas indicate when the input is permitted to change for predictable output performance. 1/f MAX (L) t (H) ...
Page 7
Philips Semiconductors 4-bit cascadable shift register (3-State) TEST CIRCUIT AND WAVEFORMS OUT PULSE D.U.T. GENERATOR Test Circuit for 3-State Outputs and Totem-Pole Output (Qs) SWITCH POSITION TEST SWITCH t closed PLZ ...