cbtv4020 NXP Semiconductors, cbtv4020 Datasheet

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cbtv4020

Manufacturer Part Number
cbtv4020
Description
20-bit Ddr Sdram 2 1 Mux
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
cbtv4020EE/G,118
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. General description
2. Features
This 20-bit bus switch is designed for 2.3 V to 2.7 V V
input levels.
Each host port pin is multiplexed to one of two DIMM port pins. When the SEL pin is HIGH
the A DIMM port is turned on and the B DIMM port is off. The ON-state connects the host
port to the DIMM port through a 20
high-impedance state exists between the Host and disabled DIMM. The DIMM port is
terminated with a 100
turned on and the A DIMM port is off.
The part incorporates a very low crosstalk design. It has a very low skew between outputs
(< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optimal
performance in DDR data bus applications.
Each switch has been optimized for connection to 1-bank or 2-bank DIMMs.
The low internal RC time constant of the switch (20
made with minimal propagation delay.
The CBTV4020 is characterized for operation from 0 C to +85 C.
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CBTV4020
20-bit DDR SDRAM 2 : 1 MUX
Rev. 03 — 4 April 2008
SEL signal is SSTL_2 compatible
Optimized for use in Double Data Rate (DDR) SDRAM applications
Designed to be used with 400 Mbit/s 200 MHz DDR data bus
Switch ON resistance is designed to eliminate the need for series resistor to DDR
SDRAM
R
Internal 100
Low differential skew
Matched rise/fall slew rate
Low crosstalk
One DIMM select control line
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 1500 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
ON
~ 20
pull-down resistors on DIMM side when path is disabled
resistor to ground. When the SEL pin is LOW the B DIMM port is
nominal series resistance. When the port is off a
DD
7 pF) allows data transfer to be
operation and SSTL_2 select
Product data sheet

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cbtv4020 Summary of contents

Page 1

... DDR data bus applications. Each switch has been optimized for connection to 1-bank or 2-bank DIMMs. The low internal RC time constant of the switch (20 made with minimal propagation delay. The CBTV4020 is characterized for operation from + Features I SEL signal is SSTL_2 compatible ...

Page 2

... Load capacitance = 7 pF. This parameter is not production Description plastic thin fine-pitch ball grid array package; 72 balls; body DHn SEL Logic diagram (positive logic) Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX Min Typ Max Unit [1] - 140 ...

Page 3

... DH2 DH3 DB3 J DA2 DB2 DA3 DA4 K Transparent top view. Empty cell indicates no ball present at that location. TFBGA72 ball mapping Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX CBTV4020EE 002aad695 Transparent top view ...

Page 4

... C5, C6, D2, D9, G2, G9, H5, H6 E8, F3 J10 G10 E10 C10 A10 Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX Description host ports select ground positive supply voltage A DIMM ports © NXP B.V. 2008. All rights reserved ...

Page 5

... B DIMM port A DIMM port = 100 to GND host port = A DIMM port B DIMM port = 100 to GND Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX Description A DIMM ports (continued) B DIMM ports logic)”. © NXP B.V. 2008. All rights reserved ...

Page 6

... Operating conditions Parameter Conditions supply voltage HIGH-level input voltage DIMM port and host (SEL) LOW-level input voltage DIMM port and host (SEL) ambient temperature operating in free air Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX Min 0.5 < [1] 0.3 [1] 0.5 ...

Page 7

... SEL to output DAn/DBn or DHn any output to any output; Figure 7 difference of rising edge propagation delay and falling edge propagation delay; Figure 8 7 pF. Load capacitance = 7 pF. This parameter is not production Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX Min Typ - - - - ...

Page 8

... PZL output DHn 1. PZH output DHn (2) 1. open 002aac820 Fig 8. Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX SEL 1. PZH output 1.25 V The output is HIGH except when disabled by the SEL control. Output enable and disable times 2.5 V 1.25 V ...

Page 9

... Test circuit, DHn to DAn/DBn from output under test 30 pF Test data are given in Table 9. Test data Load Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX 2.5 ns 500 002aac817 open 500 ...

Page 10

... 6.1 6.1 0.5 4.5 4.5 0.15 5.9 5.9 REFERENCES JEDEC JEITA MO-195 - - - Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX detail 0.08 0.05 0.1 EUROPEAN PROJECTION SOT761-1 y ISSUE DATE 02-04-10 © NXP B.V. 2008. All rights reserved. ...

Page 11

... Solder bath specifications, including temperature and impurities CBTV4020_3 Product data sheet Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX © NXP B.V. 2008. All rights reserved ...

Page 12

... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 12. Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX Figure 12) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...

Page 13

... Human Body Model Machine Model Pulse Repetition Rate Resistor-Capacitor network Synchronous Dynamic Random Access Memory Stub Series Terminated Logic for 2.5 V Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX peak temperature time 001aac844 © NXP B.V. 2008. All rights reserved ...

Page 14

... Table 8 “Dynamic characteristics”) information”: deleted type number CBTV4020EE Figure 2 “Pin configuration for TFBGA72” description”: expanded to detail pin assignments values”: : changed “S pin” to “SEL pin” ...

Page 15

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX © NXP B.V. 2008. All rights reserved ...

Page 16

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CBTV4020 All rights reserved. Date of release: 4 April 2008 Document identifier: CBTV4020_3 ...

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