at49lw040 ATMEL Corporation, at49lw040 Datasheet
at49lw040
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at49lw040 Summary of contents
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... Industry-standard Packages – (40-lead TSOP or 32-lead PLCC) Description The AT49LW040 is a Flash memory device designed to be compatible with the Intel 82802AC and the Intel 82802AB Firmware Hub (FWH) devices for PC-Bios Applica- tion. A feature of the AT49LW040 is the nonvolatile memory core. The high- performance memory is arranged in eight 64-Kbyte sectors (see page 11) ...
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... Firmware Hub Interface Address/Address Multiplexed Interface Block Diagram AT49LW040 2 between the interfaces. The interface mode needs to be selected prior to power-up or before return from reset (RST or INIT low to high transition). An internal Command User Interface (CUI) serves as the control center between the two device interfaces (FWH and A/A Mux) and internal operation of the nonvolatile memory ...
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... FWH mode. Any ID pins that are pulled high will exhibit a leakage current of approximately 200 µA. Any pins intended to be low may be left to float single FWH system, all may be left floating. A/A Mux = A[3:0] AT49LW040 + 0.3V max, unless otherwise noted ...
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... PP V SUPPLY CC GND SUPPLY V SUPPLY CCa AT49LW040 4 Interface A/A Mux Name and Function X FWH GENERAL PURPOSE INPUTS: These individual inputs can be used for additional board flexibility. The state of these pins can be read through FWH registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain at the same level until the end of the read cycle ...
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... FWH[3:0] signal lines on the next clock and monitor the bus for new cycle information. RESET: RST or INIT at VIL initiates a device reset. In read mode, RST or INIT low dese- lects the memory, places output drivers in a high-impedance state, and turns off all AT49LW040 and V requirements. ...
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... FWH memory may be providing status information instead of memory array data). CYCLE TYPES: There are two types of cycles that are supported by the AT49LW040: FWH Memory Read and FWH Memory Write. FWH Memory Read or Write cycles start with a preamble. ...
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... SYNC) on FWH[3:0] until it is ready. When ready, it will drive “0000b”. Valid values for this field are shown in Table 4. Table 4. Valid SYNC Values Bits[3:0] Indication 0000 Ready: SYNC achieved with no error. 0101 Short Wait: Part indicating wait states. AT49LW040 7 ...
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... MADDR 10 MSIZE 11 TAR0 12 TAR1 WSYNC 15 RSYNC 16 DATA 17 DATA 18 TAR0 19 TAR1 Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LW040 8 MADDR MSIZE TAR SYNC(3) PREAMBLE (1) Field Contents FWH[3:0] FWH[3:0] Direction 1101b IN 0000b IN to 1111b YYYY IN 0000b (1 byte) ...
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... The FWH outputs the values 0000, indicating that it has received data or a Flash command. 1111b OUT The FWH Flash memory drives FWH0 - FWH 3 to 1111b to then Float indicate a turnaround cycle. Float then The FWH Flash memory floats its outputs, the master (ICH) IN takes control of FWH3 - FWH0. AT49LW040 SYNC TAR 9 ...
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... Response to Invalid Fields Bus Abort AT49LW040 10 OUTPUT DISABLE: When the FWH is not selected through a FWH read or write cycle, the FWH interface outputs (FWH[3:0]) are disabled and will be placed in a high-imped- ance state. During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: • ...
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... A series of registers are available in the FWH to provide software read and write locking and GPI feedback. These registers are accessible through standard addressable mem- ory space. REGISTERS: The AT49LW040 has two types of registers: sector-locking registers and general-purpose input registers. The two types of registers appear at their respective address locations in the 4 GB system memory map. ...
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... Table 7. Sector-locking Registers for AT49LW040 Register Name Sector Size LR0 64K LR1 64K LR2 64K LR3 64K LR4 64K LR5 64K LR6 64K LR7 64K FGPI-REG Table 8. Function of Sector-locking Bits Bit Function 7:3 Reserved Read Lock Prevents read operations in the sector where set. ...
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... FGPI[4] Reads status of general-purpose input pin (PLCC-30/TSOP-7) 3 FGPI[3] Reads status of general-purpose input pin (PLCC-3/TSOP-15) 2 FGPI[2] Reads status of general-purpose input pin (PLCC-4/TSOP-16) 1 FGPI[1] Reads status of general-purpose input pin (PLCC-5/TSOP-17) 0 FGPI[0] Reads status of general-purpose input pin (PLCC-6/TSOP-18) AT49LW040 13 ...
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... It is important to note that when the TBL pin is held low, it will protect all four of the sectors mentioned above. Moreover, there is only one general-purpose register which will control the write/read status of the entire 64-Kbyte region. 8. SRD = Data Read from Status Register. AT49LW040 14 1st Bus Cycle Operation ...
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... SECTOR ERASE: Before a byte can be programmed, it must be erased. The erased state of the memory bits is a logical “1”. Since the AT49LW040 does not offer a com- plete chip erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second falling edge of the WE will be erased, provided the given sector is not protected ...
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... B0 is reserved for future use and should be masked out when polling the status register AT49LW040 16 After writing this command, all subsequent read operations will return data from the sta- tus register until another valid command is written. The Read Status Register command ...
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... The AT49LW040 is designed to offer a parallel programming mode for faster factory programming. This mode, called A/A Mux Mode, is selected by having this IC pin high. The IC pin is pulled down internally in the AT49LW040 modest current should be expected to be drawn (see Table 1 on page 3 for further information). Four control pins dictate data flow in and out of the component: R/C, OE, WE, and RST ...
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... Refer to PCI spec. 3. Inputs are not “5-volt safe.” may be changed on IC and ID pins (up to 200 µA) if pulled against internal pull-downs. Refer to the pin descriptions not violate processor or chipset specifications regarding the INIT pin voltage. AT49LW040 18 *NOTICE: (1)(2) Test Condition (1) ...
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... CC CC CLK MHz Any internal operation in progress OUT ( 3.0 - 3.6V PP per the PCI output V and V spec Memory Core + I FWH Interface AT49LW040 Min 3.0 1.5 1.5 (3) , FWH4 = (3) IL (3) Max, (2) Max Units 3 (4) 100 µA ( (4) ...
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... Notes: 1. PCI components must work with any clock frequency between nominal DC and 33 MHz. Frequencies less than16 MHz may be guaranteed by design rather than testing. 2. Applies only to rising edge of signal. Clock Waveform AT49LW040 20 Condition 0 < V 0.3 V OUT CC 0.3 V < V <0 ...
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... Reset Active Time after Power Stable Reset Active Time after CLK Stable (2) Reset Active to Output Float Delay CLK V TEST t VAL FWH[3:0] (Valid Output Data) FWH[3:0] (Float Output Data) t OFF CLK t SU Inputs Valid AT49LW040 Min 100 ...
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... AC Waveform for Reset Operation V IH RST V IL Sector Programming Times Parameter (2) Byte Program Time (2) Sector Program Time (2) Sector Erase Time Notes: 1. Typical values measured Excludes system-level overhead. AT49LW040 22 of overdrive over this CC t PLPH 3.3V V (1) Typ 30.0 2.0 0.8 = +25 C and nominal voltages. A Value ...
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... GND out min min min this specification is not CC (1)(2) t PLRH t PLPH AT49LW040 Min Max 0 -0.5 0.8 +10 = -2.5 mA 0.85 V min CC = -100 µ 0 0 Min Max 100 20 on PPH1 Unit + 0 ...
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... PHAV RST V IL AT49LW040 24 (1)( after the rising edge of R/C without impact on t GLQV . CC t AVAV Row Address Column Address Stable Stable t t CLAX AVCH t CHAX t CHQV High-Z t GLQX Min Max 250 ...
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... AVCL AVCH t CLAX t t PHWL WHWL t WLWH t WHDX t DVWH VPWH AT49LW040 Min Max 1 100 100 50 100 CHAX t CHWH t WHGL Valid D IN SRD t WHRL t ...
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... AT49LW040 Ordering Information I (mA) CC Active Standby 67 0.10 32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Thin Small Outline Package (TSOP) AT49LW040 26 Ordering Code Package AT49LW040-33JC AT49LW040-33TC Package Type Operation Range 32J Extended Commercial 40T ( 3342A–FLASH–6/03 ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3342A–FLASH–6/03 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) AT49LW040 0.318(0.0125) 0.191(0.0075 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 3.175 – ...
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... This package conforms to JEDEC reference MO-142, Variation CD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49LW040 28 PIN SEATING PLANE ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...