at49lw040 ATMEL Corporation, at49lw040 Datasheet - Page 6

• Manufacturer Part Number: at49lw040
• Description: At49lw040 4-megabit Firmware Hub Flash Memory
• Manufacturer: ATMEL Corporation

6
AT49LW040
internal circuits. RST or INIT must be held low for time t
tion). The FWH resets to read array mode upon return from reset, and all sectors are set
to default (locked) status regardless of their locked state prior to reset.
Driving RST or INIT low resets the device, which resets the sector lock registers to their
default (write-locked) condition. A reset time (t
INIT switching high until outputs are valid. Likewise, the device has a wake time (t
A/A Mux) from RST or INIT high until writes to the CUI are recognized. A reset latency
will occur if a reset procedure is performed during a programming or erase operation.
During sector erase or program, driving RST or INIT low will abort the operation under-
way, in addition to causing a reset latency. Memory contents being altered are no longer
valid, since the data may be partially erased or programmed.
It is important to assert RST or INIT during system reset. When the system comes out of
reset, it will expect to read from the memory array of the device. If a system reset occurs
with no FWH reset (this will be hardware dependent), it is possible that proper CPU ini-
tialization will not occur (the FWH memory may be providing status information instead
of memory array data).
CYCLE TYPES: There are two types of cycles that are supported by the AT49LW040:
FWH Memory Read and FWH Memory Write. FWH Memory Read or Write cycles start
with a preamble.
PREAMBLE: The preamble consists of a START, IDSEL, 28-bit Address and MSIZE
fields. The preamble is shown in Figure 1. The preamble begins with FWH4 going low
and a START field driven on FWH[3:0]. For FWH Memory Read cycles, the START field
must be 1101b; for FWH Memory Write cycles, the START field must be 1110b. Follow-
ing the START field is the IDSEL field. This field acts like a chip select in that it indicates
which device should respond to the current transaction. The next seven clocks are the
28-bit address, which tell from where to begin reading or writing in the selected device.
Next, an MSIZE value of 0 indicates the master is requesting a single byte.
Figure 1. FWH Memory Cycle Preamble
START: This one-clock field indicates the start of a cycle. It is valid on the last clock that
FWH4 is sampled low. The two start fields that are used for the cycle are shown in Table
3. If the start field that is sampled is not one of these values, then the cycle attempted is
not an FWH memory cycle. It may be a valid memory cycle that the FWH component
may wish to decode, i.e., it may be of the LPC memory cycle variety.
Table 3. Start Fields
IDSEL (DEVICE SELECT): This one-clock field is used to indicate which FWH compo-
nent is being selected. The four bits transmitted over FWH[3:0] during this clock are
compared with values strapped onto pins [ID3:ID0] on the FWH component. If there is a
FWH[3:0]
1101b
1110b
FWH3 - FWH0
FWH4
CLK
START
Indication
FWH Memory Read
FWH Memory Write
IDSEL
PHQV
28-BIT ADDRESS
A/A Mux) is required from RST or
PLPH
(A/A Mux and FWH opera-
3342A–FLASH–6/03
MSIZE
PHRH