at49lw040 ATMEL Corporation, at49lw040 Datasheet - Page 15

• Manufacturer Part Number: at49lw040
• Description: At49lw040 4-megabit Firmware Hub Flash Memory
• Manufacturer: ATMEL Corporation

3342A–FLASH–6/03
READ ARRAY: Upon initial device power-up and after exit from reset, the device
defaults to read array mode. This operation is also initiated by writing the Read Array
command. The device remains enabled for reads until another command is written.
Once the internal state machine (WSM) has started a block erase or program operation,
the device will not recognize the Read Array Command until the operation is completed.
The Read Array command functions independently of the V
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel.
Following the Product ID Entry command, read cycles from the addresses shown in
Table 11 retrieve the manufacturer and device code. To exit the product identification
mode, any valid command can be written to the device. The Product ID Entry command
functions independently of the V
Table 11. Identifier Codes
SECTOR ERASE: Before a byte can be programmed, it must be erased. The erased
state of the memory bits is a logical “1”. Since the AT49LW040 does not offer a com-
plete chip erase, the device is organized into multiple sectors that can be individually
erased. The Sector Erase command is a two-bus cycle operation. The sector whose
address is valid at the second falling edge of the WE will be erased, provided the given
sector is not protected.
Successful sector erase requires that the corresponding sector’s Write Lock bit be
cleared and the corresponding write-protect pin (TBL or WP) be inactive. If sector erase
is attempted when the sector is locked, the sector erase will fail, with the reason for fail-
ure in the status register.
Successful sector erase only occurs when V
attempted at V
BYTE PROGRAMMING: The device is programmed on a byte-by-byte basis. Program-
ming is accomplished via the internal device command register and is a two-bus cycle
operation. The programming address and data are latched in the second bus cycle. The
device will automatically generate the required internal programming pulses. Please
note that a “0” cannot be programmed back to a “1”; only an erase operation can convert
“0”s to “1”s.
After the program command is written, the device automatically outputs the status regis-
ter data when read. When programming is complete, the status register may be
checked. If a program error is detected, the status register should be cleared before cor-
rective action is taken by the software. The internal WSM verification Error Checking
only detects “1”s that do not successfully program to “0”s.
Reliable programming only occurs when V
attempted at V
A successful program operation also requires that the corresponding sector’s Write Lock
bit be cleared, and the corresponding write-protect pin (TBL or WP) be inactive. If a pro-
gram operation is attempted when the sector is locked, the operation will fail.
READ STATUS REGISTER: The status register may be read to determine when a sec-
tor erase or program completes and whether the operation completed successfully. The
status register may be read at any time by writing the Read Status Register command.
Code
Manufacturer Code
Device Code
PP
PP
V
V
PPH1
PPH1
erratic results may occur.
erratic results may occur.
Address (AID)
000000
000001
PP
voltage.
PP
PP
= V
= V
PPH1
PPH1
. If the program operation is
PP
Data
1F
E0
. If the erase operation is
voltage.
AT49LW040
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