at49lw040 ATMEL Corporation, at49lw040 Datasheet - Page 17

• Manufacturer Part Number: at49lw040
• Description: At49lw040 4-megabit Firmware Hub Flash Memory
• Manufacturer: ATMEL Corporation

A/A Mux Interface
3342A–FLASH–6/03
The following information applies only to the AT49LW040 when in A/A Mux Mode. Infor-
mation on FWH Mode (the standard operating mode) is detailed earlier in this
document. Electrical characteristics in A/A Mux Mode are provided on pages starting
from page 27.
The AT49LW040 is designed to offer a parallel programming mode for faster factory
programming. This mode, called A/A Mux Mode, is selected by having this IC pin high.
The IC pin is pulled down internally in the AT49LW040, so a modest current should be
expected to be drawn (see Table 1 on page 3 for further information). Four control pins
dictate data flow in and out of the component: R/C, OE, WE, and RST. R/C is the A/A
Mux control pin used to latch row and column addresses. OE is the data output control
pin (I/O0 - I/O7), drives the selected memory data onto the I/O bus, when active WE and
RST must be at V
BUS OPERATION: All A/A Mux bus cycles can be conformed to operate on most auto-
mated test equipment and PROM programmers.
Bus Operations
Notes:
OUTPUT DISABLE/ENABLE: With OE at a logic-high level (V
disabled. Output pins I/O0 - I/O7 are placed in the high-impedance state. With OE at a
logic-low level (V
in a output-drive state.
ROW/COLUMN ADDRESSES: R/C is the A/A Mux control pin used to latch row (A0 -
A10) and column addresses (A11 - A18). R/C latches row addresses on the falling edge
and column addresses on the rising edge.
RDY/BUSY: An open drain Ready/Busy output pin provides a hardware method of
detecting the end of a program or erase operation. RDY/Busy is actively pulled low dur-
ing the internal program and erase cycles and is released at the completion of the cycle.
Mode
Read
Output Disable
Product ID Entry
Write
(1)(2)(6)
(4)(5)(6)
1. When V
2. X can be V
3. See Table 11 on page 15 for Product ID Entry data and addresses.
4. Command writes involving sector erase or program are reliably executed when V
5. Refer to “A/A Mux Read-only Operations” for valid D
6. V
supply pin. See the “DC Characteristics” for V
V
ers: V
PPH1
IH
(6)
and V
(6)
IL
and V
IL
IH
min = 0.5V, V
), the device outputs are enabled. Output pins I/O0 - I/O7 are placed
PP
.
IL
IL
refer to the DC characteristics associated with Flash memory output buff-
V
CC
RST
or V
PPLK
V
V
V
V
IH
IH
IH
IH
= V
IH
, the memory contents can be read, but not altered.
CC
for control and address input pins and V
IL
± 0.3V.
max = 0.8V, V
OE
V
V
V
V
IH
IH
IL
IL
WE
V
V
V
V
IH
IH
IH
IH
IL
min = 2.0V, V
PPLK
Address
(3)
X
X
X
and V
IN
IH
during a write operation.
max = V
PPH1
IH
), the device outputs are
AT49LW040
PPLK
V
voltages.
X
X
X
X
PP
CC
or V
+ 0.5V.
PPH1
I/O0 - I/O7
for the VPP
High-Z
Note 3
D
D
OUT
IN
PP
17
=