at49lw040 ATMEL Corporation, at49lw040 Datasheet - Page 2

• Manufacturer Part Number: at49lw040
• Description: At49lw040 4-megabit Firmware Hub Flash Memory
• Manufacturer: ATMEL Corporation

Firmware Hub Interface
Address/Address
Multiplexed Interface
Block Diagram
2
AT49LW040
between the interfaces. The interface mode needs to be selected prior to power-up or
before return from reset (RST or INIT low to high transition).
An internal Command User Interface (CUI) serves as the control center between the two
device interfaces (FWH and A/A Mux) and internal operation of the nonvolatile memory.
A valid command sequence written to the CUI initiates device automation.
The VPP pin gives complete data protection when V
together for a simple, low-power 3V design. Programming board solutions should design
such that V
ming current may be drawn from either pin.
The Firmware Hub (FWH) interface is designed to work with the I/O Controller Hub
(ICH) during platform operation.
The FWH interface consists primarily of a five-signal communication interface used to
control the operation of the device in a system environment. The buffers for this inter-
face are PCI compliant. To ensure the effective delivery of security and manageability
features, the FWH interface is the only way to get access to the full feature set of the
device. The FWH interface is equipped to operate at 33 MHz, synchronous with the PCI
bus.
The A/A Mux interface is designed as a programming interface for OEMs to use during
motherboard manufacturing or component pre-programming.
The A/A Mux refers to the multiplexed row and column addresses in this interface. This
approach is required so that the device can be tested and programmed quickly with
automated test equipment (ATE) and PROM programmers in the OEM’s manufacturing
flow. This interface also allows the device to have an efficient programming interface
with potentially large future densities, while still fitting into a 32-pin package. Only basic
reads, programming, and erase of the nonvolatile memory sectors can be performed
through the A/A Mux interface. In this mode FWH features, security features and regis-
ters are unavailable. A row/column (R/C) pin determines which set of addresses “rows
or columns” are latched.
PP
draws from the same supply as V
FGPI (4:0)
I/O7 - I/O0
FWH (4:0)
A10 - A0
ID (3:0)
RY/BY
CLK
TBL
INIT
R/C
WE
WP
OE
INTERFACE
INTERFACE
A/A MUX
FWH
CC
, and should assume that full program-
PP
V
PPLK
. V
RST
CC
CONTROL
ARRAY
LOGIC
FLASH
and V
IC
3342A–FLASH–6/03
PP
can be tied