m95512-dr STMicroelectronics, m95512-dr Datasheet
m95512-dr
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m95512-dr Summary of contents
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... Compatible with SPI bus serial interface (Positive clock SPI modes): – M95512-W and M95512-R: standard SPI 512 Kbit EEPROM – M95512-DR: standard SPI 512 Kbit EEPROM with Identification page ■ Single supply voltage: – 2 5.5 V for M95512-W – 1 5.5 V for M95512-R and M95512-DR ■ ...
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... Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR ...
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... Read Identification Page (available only in M95512-DR devices 6.8 Write Identification Page (available only in M95512-DR devices 6.9 Read Lock Status (available only in M95512-DR devices 6.10 Lock ID (available only in M95512-DR devices ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 29 8 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 ...
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... Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 8. Operating conditions (M95512-W device grade Table 9. Operating conditions (M95512-W device grade Table 10. Operating conditions (M95512-R and M95512-DR Table 11. AC measurement conditions Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 13. DC characteristics (current M95512-W products Table 14. DC characteristics (new M95512-W products Table 15 ...
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... M95512-W, M95512-R, M95512-DR List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO8, TSSOP8 and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 ...
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... Description 1 Description The M95512-W, M95512-R and M95512-DR are electrically erasable programmable memory (EEPROM) devices accessed by a high-speed SPI-compatible bus. In the rest of the document these devices are referred to as M95512, unless otherwise specified. The memory array is organized as 65536 × 8 bit. The device is accessed by a simple serial interface that is SPI-compatible ...
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... M95512-W, M95512-R, M95512-DR Figure 2. SO8, TSSOP8 and UFDFPN8 connections 1. See Section 11: Package mechanical data for package dimensions, and how to identify pin-1. Doc ID 11124 Rev 12 Description 7/47 ...
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... Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/47 must be held stable and within the specified valid range: CC Table 13 and Table 15). These signals are described next. Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512- ...
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... M95512-W, M95512-R, M95512-DR 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions. ...
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... SDI SCK SPI Memory R R Device S W HOLD Figure 3) ensures that no device is selected if the Bus requirement is met. SHCH Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512- SPI Memory SPI Memory R Device Device HOLD ...
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... M95512-W, M95512-R, M95512-DR 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C) ...
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... CC CC Table 8 and Table 10). (min rises continuously from V CC and Table 10 and the rise time must not vary faster than 1 V/µs. Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR CC Table 8 and / reaches a valid and CC (max)] range defined in Table ...
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... M95512-W, M95512-R, M95512-DR 4.1.4 Power-down During power-down (continuous decrease in V defined in Table 8 ● deselected (Chip Select (S) should be allowed to follow the voltage applied on V ● in Standby Power mode (that is there should not be any internal write cycle in progress). 4.2 Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode ...
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... The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus. Table 2. Write-protected block size Status register bits BP1 14/47 M95512-W, M95512-R, M95512-DR Section 6.3: Read Status Register (RDSR) Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 ...
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... M95512-W, M95512-R, M95512-DR 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD Figure 6. High Voltage Control Logic I/O Shift Register Address Register and Counter Doc ID 11124 Rev 12 Memory organization Generator Data Register Status Register 1 Page X Decoder Size of the Read only ...
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... Write to Memory Array Reads the page dedicated to identification. Writes the page dedicated to identification. Reads the lock status of the Identification Page. Locks the Identification page in read-only mode. Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR Table 3. Table 3), the device automatically Instruction format 0000 0110 ...
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... M95512-W, M95512-R, M95512-DR 6.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state ...
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... Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5. Status register format b7 SRWD Status Register Write Protect 18/47 Table 5) becomes protected against Write Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR Figure 9. BP1 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit b0 WIP ...
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... M95512-W, M95512-R, M95512-DR Figure 9. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Doc ID 11124 Rev 12 Instructions Status Register Out MSB 7 AI02031E ...
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... Figure 10. Write Status Register (WRSR) sequence 20/47 (specified in Table complete. W Table Instruction 7 High Impedance MSB Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR and Table 18). The instruction sequence Status Register AI02282D ...
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... M95512-W, M95512-R, M95512-DR Table 6. Protection modes W SRWD Signal Bit 1 0 Software 0 0 Protected 1 1 Hardware 0 1 Protected 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...
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... Chip Select (S) is first driven 16-Bit Address MSB Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512- Data Out 1 Data Out MSB AI01793D ...
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... M95512-W, M95512-R, M95512-DR 6.6 Write to Memory Array (WRITE) As shown in Figure low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data ...
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... Address Data Byte 2 Data Byte Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512- Data Byte Data Byte ...
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... M95512-W, M95512-R, M95512-DR 6.7 Read Identification Page (available only in M95512-DR devices) As shown in Figure first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A7] are Don't Care, and the data byte pointed to by [A6:A0] is shifted out on Serial Data output (Q). ...
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... Instructions 6.8 Write Identification Page (available only in M95512-DR devices) As shown in Figure first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in on Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A7] are Don't Care, the [A6:A0] address bits define the byte address inside the identification page ...
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... M95512-W, M95512-R, M95512-DR 6.9 Read Lock Status (available only in M95512-DR devices) The Read Lock Status instruction is used to read the lock status. To send this instruction to the device, Chip Select (S) first has to be driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q ‘ ...
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... Chip Select (S) being driven high byte boundary (after the eighth bit, b0, of the last data byte that was latched in) ● if the Identification page is locked by the Lock Status bit Figure 17. Lock ID sequence 28/47 M95512-W, M95512-R, M95512-DR Doc ID 11124 Rev 12 ...
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... It is therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95512-W, M95512-R and M95512-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets. ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100 pF, R1=1500 , R2=500 ) 30/47 M95512-W, M95512-R, M95512-DR Table 7 may cause permanent damage to Parameter Doc ID 11124 Rev 12 Min ...
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... Ambient operating temperature (device grade 6) A Table 9. Operating conditions (M95512-W device grade 3) Symbol V Supply voltage CC T Ambient operating temperature (device grade 6) A Table 10. Operating conditions (M95512-R and M95512-DR) Symbol V Supply voltage CC T Ambient operating temperature A Table 11. AC measurement conditions Symbol C Load capacitance ...
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... 2.5 V < 2.5 V and and 2.5 V and and I CC Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR Min. Max 2 Min. Max ± ± MHz ...
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... IH V Output low voltage OL V Output high voltage OH 1. New products are identified by process letter K. 2. Characterized value, not tested in production. Table 15. DC characteristics (current and new M95512-R and M95512-DR products) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) ...
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... Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR = –40 to 125 °C (device grade 3) A Min. Max. D. ...
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... M95512-W, M95512-R, M95512-DR Table 17. AC characteristics (New Test conditions: V Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH t S not active hold time ...
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... DC and AC parameters Table 18. AC characteristics (current and new M95512-R and M95512-DR products) Test conditions: V Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time ...
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... M95512-W, M95512-R, M95512-DR Figure 19. Serial input timing S tCHSL C tDVCH D Q Figure 20. Hold timing HOLD tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 11124 Rev 12 DC and AC parameters tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c ...
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... DC and AC parameters Figure 21. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN 38/47 M95512-W, M95512-R, M95512-DR tCH tCHCL tCL tQLQH tQHQL Doc ID 11124 Rev 12 tSHSL tSHQZ AI01449f ...
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... M95512-W, M95512-R, M95512-DR 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 22. SO8N – 8 lead plastic small outline, 150 mils body width, package outline A2 1 ...
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... Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512- TSSOP8AM (1) inches Typ Min Max 0.0472 0.0020 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 ...
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... M95512-W, M95512-R, M95512-DR Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 mm, package outline 1. Drawing is not to scale. Table 21. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 .mm, package mechanical data ...
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... The process letters only appear in the product ordering codes of device grade 3 devices. For other devices only given here as an indication of how to differentiate current from new products. To identify current from new devices, please contact your nearest ST sales office. 42/47 M95512 (1) . ® (RoHS compliant) Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR – /AB ...
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... For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 23. Available M95512 products (package, voltage range, temperature grade) Package SO8 (MN) TSSOP (DW) UFDFPN8 (MB) Table 24. Available M95512-DR products (package, voltage range, temperature grade) Package SO8 (MN) TSSOP (DW) M95512-W 2 5.5 V Range 6, range 3 Range 6 ...
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... Figure 20: Hold timing. Power On Reset Array Addresses modified in Operating Temperature value added in 6.0 ratings. Supply Current (I characteristics (current M95512-W Table 18: AC characteristics (current and new M95512-R and M95512-DR products). Document status changed to Datasheet. Doc ID 11124 Rev 12 M95512-W, M95512-R, M95512-DR Changes (min) improved ...
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... Table 23: Available M95512 products (package, voltage range, temperature grade) added. Small text changes. M95512-DR part number added (see products (package, voltage range, temperature 10 New M95512-W, M95512-R and M95512-DR products operating MHz added (preliminary data). UFDFPN8 package added (see Doc ID 11124 Rev 12 Revision history Changes ...
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... Section 6.7: Read Identification Page (available only in M95512-DR devices) 11 – Section 6.8: Write Identification Page (available only in M95512-DR devices) – Section 6.9: Read Lock Status (available only in M95512-DR devices) – Section 6.10: Lock ID (available only in M95512-DR devices) Data related to new products are no longer preliminary. 12 Note 2 updated in ...
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... M95512-W, M95512-R, M95512-DR Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...