m95512-dr STMicroelectronics, m95512-dr Datasheet - Page 20

• Manufacturer Part Number: m95512-dr
• Description: 512kbit Serial Spi Bus Eeprom With High Speed Clock
• Manufacturer: STMicroelectronics

Instructions
6.4
20/47
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before a WRSR instruction can be accepted, a Write Enable (WREN) instruction
must have been executed.
The Write Status Register (WRSR) instruction is issued by driving Chip Select (S) low,
sending the instruction code and the data byte on Serial Data input (D) and driving Chip
Select (S) high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C)
that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock
(C). Otherwise, the Write Status Register (WRSR) instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write
cycle whose duration is t
shown in
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t
also reset when the Write cycle t
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 and SRWD bits:
●
●
The contents of the SRWD and BP1, BP0 bits are updated upon completion of the WRSR
instruction (after t
The Write Status Register (WRSR) instruction has no effect on Status Register bits b6, b5,
b4, b1, b0. They are always read as 0.
Figure 10. Write Status Register (WRSR) sequence
The Block Protect (BP1, BP0) bits define the size of the area to be treated as read-only,
as defined in
The SRWD bit (Status Register Write Disable bit), depending on the signal applied on
the Write Protect pin (W), allows the user to set or reset the write protection mode of
the Status Register. When the Status Register is in the Write-protected mode, the Write
Status Register (WRSR) instruction is not executed.
Figure
S
C
D
Q
W
, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
10.
W
Table
).
0
6.
W
1
High Impedance
(specified in
2
Instruction
Doc ID 11124 Rev 12
3
W
4
is complete.
5
Table 16
6
7
MSB
7
8
6
and
9 10 11 12 13 14 15
5
Register In
Table
4
Status
M95512-W, M95512-R, M95512-DR
3
18). The instruction sequence is
2
1
0
AI02282D