cy62127dv30 Cypress Semiconductor Corporation., cy62127dv30 Datasheet

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cy62127dv30

Manufacturer Part Number
cy62127dv30
Description
1-mb 64k X 16 Static Ram
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-05229 Rev. *H
Features
Functional Description
The CY62127DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
Note:
Logic Block Diagram
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
• Temperature Ranges
• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62127BV
• Ultra-low active power
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Available in Pb-Free and non Pb-Free 48-ball FBGA and
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = f
a 44-lead TSOP Type II packages
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
A
A
A
A
A
A
A
A
A
A
A
10
10
3
2
1
0
9
8
7
6
5
4
[1]
MAX
Pow er -Down
Circuit
COLUMN DECODER
DATA IN DRIVERS
198 Champion Court
RAM Array
2048 x 512
64K x 16
®
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH) or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes
.
0
through I/O
1-Mb (64K x 16) Static RAM
CE
15
San Jose
). If Byte High Enable (BHE) is LOW, then data
BHE
BLE
15
8
) are placed in a high-impedance state
through I/O
,
CA 95134-1709
0
I/O
I/O
to I/O
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
7
7
15
. If Byte High Enable (BHE) is
15
0
Revised June 19, 2006
) is written into the location
through A
CY62127DV30
0
15
through I/O
).
8
408-943-2600
to I/O
15
. See
7
), is
0
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cy62127dv30 Summary of contents

Page 1

... Available in Pb-Free and non Pb-Free 48-ball FBGA and a 44-lead TSOP Type II packages [1] Functional Description The CY62127DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL ...

Page 2

... Product Portfolio V Range (V) CC Product Min. Typ. Max. CY62127DV30L 2.2 3.0 3.6 CY62127DV30LL 2.2 3.0 CY62127DV30L 3.6 2.2 3.0 CY62127DV30LL 3.6 CY62127DV30L 2.2 3.0 3.6 CY62127DV30LL [2, 3] Pin Configurations FBGA (Top View BLE I/O A BHE I I/O I I/O I DNU NC I/O I ...

Page 3

... T = 25° MHz CC(typ) = Vcc+0.75V for pulse durations less than 20 ns. IH(max.) from & V must be stable at V CC(min) CC CC(min) CY62127DV30 [5] ................................ −0. 0.3V CC [6] Ambient Temperature ( –40°C to +85°C 2.2V to 3.6V –40°C to +125°C 2.2V to 3.6V –55 – ...

Page 4

... DATA RETENTION MODE DATA RETENTION MODE V V > 1. > 1.5V CC(min.) DR CC(min CDR CDR > 200 µ CC(min.) CY62127DV30 FBGA TSOP II Unit 55 76 °C °C/W 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT Unit Ω Ω Ω V .[4] Min. Typ Max ...

Page 5

... V CC(typ.) is less than less than HZCE LZCE HZBE LZBE HZOE , BHE and/or BLE = V IL CY62127DV30 CY62127DV30-70 Max. Min. Max. Unit ...

Page 6

... During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05229 Rev. *H [16,17 OHA SCE PWE DATA VALID CY62127DV30 DATA VALID Page [+] Feedback ...

Page 7

... Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS CE BHE/BLE DATA I/O DON'T CARE t HZWE Document #: 38-05229 Rev SCE PWE VALID DATA IN [20, 21 SCE PWE t SD DATA VALID IN CY62127DV30 LZWE Page [+] Feedback ...

Page 8

... Read Lower Byte Only High Z Data Out Read Upper Byte Only High Z Output Disabled High Z Output Disabled Output Disabled High Z Data In Write High Z Write Lower Byte Only Data In Write Upper Byte Only CY62127DV30 Mode Power Standby ( Standby ( Active ( ...

Page 9

... Ordering Information Speed (ns) Ordering Code 45 CY62127DV30LL-45BVXI CY62127DV30LL-45ZXI 55 CY62127DV30LL-55BVI CY62127DV30LL-55BVXI CY62127DV30LL-55ZI CY62127DV30L-55ZXI CY62127DV30LL-55ZXI CY62127DV30L-55BVXE CY62127DV30L-55ZSXE 70 CY62127DV30L-70BVI CY62127DV30LL-70BVXI CY62127DV30L-70ZI CY62127DV30LL-70ZXI Please contact your local Cypress sales representative for availability of these parts Package Diagrams TOP VIEW A1 CORNER 6.00± ...

Page 10

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 44-lead TSOP II (51-85087) CY62127DV30 51-85087-*A Page ...

Page 11

... Document History Page Document Title: CY62127DV30 MoBL Document Number: 38-05229 Orig. of REV. ECN NO. Issue Date Change ** 117690 08/27/02 *A 127311 06/13/03 *B 128341 07/22/03 *C 129000 08/29/03 *D 316039 See ECN *E 346982 See ECN *F 369955 See ECN *G 457685 See ECN *H 470383 See ECN Document #: 38-05229 Rev. *H ® 1-Mb (64K x 16) Static RAM ...

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