m48z35av-70pc6tr STMicroelectronics, m48z35av-70pc6tr Datasheet - Page 8

• Manufacturer Part Number: m48z35av-70pc6tr
• Description: 5.0v Or 3.3v, 256kbit 32kbit X 8 Zeropower Sram
• Manufacturer: STMicroelectronics

2
Note:
2.1
8/24
Operating modes
The M48Z35AV also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single power supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
approximately V
power returns.
Table 2.
1. See
X = V
Read mode
The M48Z35AV is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable)
is low. The device architecture allows ripple-through access of data from eight of 264,144
locations in the static storage array. Thus, the unique address specified by the 15 Address
Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Access time (t
signal is stable, providing that the E and G access times are also satisfied. If the E and G
access times are not met, valid data will be available after the latter of the Chip Enable
Access time (t
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before t
the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
IH
Table 10 on page 17
or V
IL
V
Operating modes
; V
SO
ELQV
SO
SO
3.0 to 3.6V
to V
AVQV
, the control circuitry connects the battery which maintains data until valid
) or Output Enable Access time (t
V
= Battery back-up switchover voltage.
V
PFD
SO
CC
, the data lines will be driven to an indeterminate state until t
(1)
for details.
(min)
AXQX
(1)
) but will go indeterminate until the next Address Access.
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
GLQV
V
V
V
W
X
X
X
IH
IH
IL
).
AVQV
CC
DQ0-DQ7
High Z
High Z
High Z
High Z
D
. As V
) after the last address input
D
OUT
IN
CC
falls below
CC
Battery back-up
CMOS standby
is out of
Standby
Power
Active
Active
Active
mode
AVQV
. If