m29dw641f STMicroelectronics, m29dw641f Datasheet - Page 41

• Manufacturer Part Number: m29dw641f
• Description: 64 Mbit 4mb X16, Multiple Bank, Boot Block 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

M29DW641F
7
7.1
7.2
Status Register
The M29DW641F has one Status Register. The Status Register provides information on the
current or previous Program or Erase Operations executed in each bank. The various bits
convey information and errors on the operation. Bus Read Operations from any address
within the Bank, always read the Status Register during Program and Erase Operations. It is
also read during Erase Suspend when an address within a block being erased is accessed.
The bits in the Status Register are summarized in
Data polling bit (DQ7)
The Data Polling bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling bit is output on DQ7 when the Status Register is read.
During Program Operations the Data Polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program Operation the memory
returns to Read mode and Bus Read Operations from the address just programmed output
DQ7, not its complement.
During Erase Operations the Data Polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase Operation the memory returns to Read
mode.
In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read Operation
within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase Operation.
Figure 7: Data polling
Address is the address being programmed or an address within the block being erased.
Toggle bit (DQ6)
The Toggle bit can be used to identify whether the Program/Erase Controller has
successfully completed its Operation or if it has responded to an Erase Suspend. The
Toggle bit is output on DQ6 when the Status Register is read.
During Program and Erase Operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read Operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle bit will output when addressing a cell within a block
being erased. The Toggle bit will stop toggling when the Program/Erase Controller has
suspended the Erase Operation.
Figure 8: Toggle
and
Figure 16
describe Toggle bit timing waveform.
flowchart, gives an example of how to use the Data Toggle bit.
flowchart, gives an example of how to use the Data Polling bit. A Valid
Table 13: Status Register
Status Register
bits.
Figure 15
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