m58wr032kl STMicroelectronics, m58wr032kl Datasheet
m58wr032kl
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m58wr032kl Summary of contents
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... M58WR016KU M58WR016KL M58WR032KU M58WR032KL M58WR064KU M58WR064KL 16-, 32- and 64-Mbit (x 16, Mux I/O, Multiple Bank, Burst) Features Supply voltage – 1 for Program, Erase and DD Read – 1 for I/O buffers DDQ – for fast Program PP Multiplexed address/data Synchronous / Asynchronous Read – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M58WRxxxKU, M58WRxxxKL 5.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 ...
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Contents 7.7 Block Protection Status bit (SR1 7.8 ...
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M58WRxxxKU, M58WRxxxKL 14 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Table 31. Top boot block addresses, M58WR016KU Table 32. Bottom boot block addresses, M58WR016KL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 33. Top boot block addresses, M58WR032KU Table 34. Bottom boot block addresses, M58WR032KL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 35. Top boot block addresses, M58WR064KU Table 36. Bottom boot block addresses, M58WR064KL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 37. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 38. ...
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M58WRxxxKU, M58WRxxxKL Table 49. Command interface states - Lock table, next state ...
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... VFBGA44 connections (top view through package Figure 3. M58WR016KU/L memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. M58WR032KU/L memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. M58WR064KU/L memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 7. X-latency and data output configuration example Figure 8. Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 9. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 10. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 11 ...
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... Figures 3, memory address space for the M58WR016KU, M58WR032KU and M58WR064KU, and at the bottom for the M58WR016KL, M58WR032KL and M58WR064KL. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed ...
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... ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Protection Register memory map. The memory is available in a VFBGA44 7.5 × 5 mm, 10 × 4 active ball array, 0.5 mm pitch package supplied with all the bits erased (set to ’1’). 10/123 M58WRxxxKU, M58WRxxxKL ≤ ...
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... NC 1. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/ DDQ V PP (1) A16-Amax W E M58WR016KU M58WR016KL G M58WR032KU M58WR032KL RP M58WR064KU M58WR064KL SSQ Description Address inputs Data input/outputs or Address inputs, Command inputs Chip Enable Output Enable ...
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Description Figure 2. VFBGA44 connections (top view through package) 12/123 M58WRxxxKU, M58WRxxxKL ...
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M58WRxxxKU, M58WRxxxKL Table 2. M58WR016KU/L bank architecture Number Parameter Bank Bank 1 Bank 2 Bank 3 Table 3. M58WR032KU/L bank architecture Number Parameter Bank Bank 1 Bank 2 Bank 3 Bank 6 Bank 7 Table 4. M58WR064KU/L bank architecture Number ...
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... Description Figure 3. M58WR016KU/L memory map Address lines ADQ0-ADQ15 and A16-A19 00000h 07FFFh Bank 3 38000h 3FFFFh 40000h 47FFFh Bank 2 78000h 7FFFFh 80000h 87FFFh Bank 1 B8000h BFFFFh C0000h C7FFFh F0000h Parameter F7FFFh Bank F8000h F8FFFh FF000h FFFFFh 14/123 M58WR016KU - Top Boot Block 32 KWord ...
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... KWord 32 KWord 8 Main Blocks Bank 3 32 KWord 32 KWord 7 Main Blocks 32 KWord 4 KWord 8 Parameter Blocks Bank 7 4 KWord Description M58WR032KL - Bottom Boot Block Address lines A20-A16 and ADQ15-ADQ0 000000h 4 KWord 000FFFh 8 Parameter Blocks 007000h 4KWord 007FFFh 008000h 32 KWord 00FFFFh 7 Main Blocks 038000h ...
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... Description Figure 5. M58WR064KU/L memory map Address lines A21-A16 and ADQ15-ADQ0 000000h 007FFFh Bank 15 038000h 03FFFFh 300000h 307FFFh Bank 3 338000h 33FFFFh 340000h 347FFFh Bank 2 378000h 37FFFFh 380000h 387FFFh Bank 1 3B8000h 3BFFFFh 3C0000h 3C7FFFh 3F0000h Parameter 3F7FFFh Bank 3F8000h 3F8FFFh 3FF000h 3FFFFFh 16/123 ...
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... Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. ...
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... Chip Enable or Output Enable 2.12 V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (Read, Program and Erase). 18/123 if the Power-Down function is enabled. Refer to DD2 and I DD2 DD3 , the device is in normal operation ...
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M58WRxxxKU, M58WRxxxKL 2.13 V supply voltage DDQ V provides the power supply to the I/O pins and enables all Outputs to be powered DDQ independently from V 2.14 V Program supply voltage both a control input and ...
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... Bus Write operations. 3.1 Bus Read Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must should be used to enable the device. Output Enable should be used to gate data onto the output ...
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... Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at V consumption is reduced to the standby level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V during a program or erase operation, the device enters Standby mode when finished ...
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... Command interface 4 Command interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation ...
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M58WRxxxKU, M58WRxxxKL 5 Command interface - Standard commands The following commands are the basic commands used to read, write to and configure the device. Refer to Table 7: Standard descriptions. 5.1 Read Array command The Read Array command returns the ...
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... Parameter Bank and the CFI memory space are not allowed (see limitations). See Appendix B: Common Flash for details on the information contained in the Common Flash Interface memory area. 5.5 Clear Status Register command The Clear Status Register command can be used to reset (set to ‘0’) error bits SR1, SR3, SR4 and SR5 in the Status Register ...
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... Program command The memory array can be programmed word-by-word. Only one Word in one bank can be programmed at any one time. If the block is protected then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. ...
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Command interface - Standard commands 5.8 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has ...
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... Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Dual operation limitations See ...
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Command interface - Standard commands 5.12 Block Lock command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two ...
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M58WRxxxKU, M58WRxxxKL Table 7. Standard commands Commands Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down ...
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... Protection Register Lock 80h M58WRxxxKU, M58WRxxxKL Address (h) Data (h) Bank Address + 00 0020 8823 (M58WR016KU) Bank Address + 01 8828 (M58WR032KU) 88C0 (M58WR064KU) 8824 (M58WR016KL) Bank Address + 01 8829 (M58WR032KL) 88C1 (M58WR064KL) 0001 0000 Block Address + 02 0003 0002 Bank Address + 03 DRC Bank Address + 05 CR 0002 Bank Address + 80 ...
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... Dual operations are not supported during Double Word Program operations and the command cannot be suspended. Typical Program times are given in Programming aborts if Reset goes to V program operation is aborted, the memory locations must be reprogrammed. See Appendix C, flowchart for using the Double Word Program command ...
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... Programming aborts if Reset goes to V program operation is aborted, the memory locations must be reprogrammed. During Quadruple Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored ...
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... Status Register will output the error. The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Factory Program 6 ...
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... Finally, after all words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase. If the Verify Phase is successfully completed the memory remains in Read Status Register mode. If the Program/Erase Controller fails to reprogram a given location, the error will be signaled in the Status Register. ...
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... It has four phases: the Setup Phase, the Load Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the Verify Phase ...
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... See the section on the Status Register for more details. If the Program and Verify Phase has successfully completed the memory returns to Read mode. If the P/E.C. fails to program and reprogram a given location, the error will be signaled in the Status Register ...
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... A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and check that the memory is ready to accept the next data number of words number of Pages to be programmed. 6. Any address within the block can be used. ...
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... The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. ...
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... Erase Status bit (SR5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly ...
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... The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive) ...
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M58WRxxxKU, M58WRxxxKL Table 10. Status Register bits Bit Name SR7 P/E.C. Status SR6 Erase Suspend Status SR5 Erase Status SR4 Program Status SR3 V Status PP Program Suspend SR2 Status SR1 Block Protection Status Bank Write Status SR0 Multiple Word ...
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... Configuration Register 8 Configuration Register The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power- Up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in X latency and the Read operation ...
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... For correct operation the X-Latency bits can only assume the values in Configuration Register. Table 11 shows how to set the X-Latency parameter, taking into account the speed class of the device and the Frequency used to read the Flash memory in Synchronous mode. Table 11. X-latency settings fmax 30 MHz ...
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... The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See Burst type definition, for the sequence of addresses output from a given starting address in each mode ...
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M58WRxxxKU, M58WRxxxKL 8.11 Burst length bits (CR2-CR0) The Burst Length bits set the number of words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, ...
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Configuration Register Table 12. Configuration Register Bit Description CR15 Read Select Bus invert CR14 configuration CR13-CR11 X-Latency CR10 Wait Polarity Data Output CR9 Configuration CR8 Wait Configuration CR7 Burst Type CR6 Valid Clock Edge Power-Down CR5 Configuration CR4 Reserved CR3 ...
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M58WRxxxKU, M58WRxxxKL Table 13. Burst type definition 4 words Start Sequen- Inter- Add tial leaved 0 0-1-2-3 0-1-2-3 1 1-2-3-0 1-0-3-2 2 2-3-0-1 2-3-0-1 3 3-0-1-2 3-2-1-0 ... 7 7-4-5-6 7-6-5-4 ... words Sequential Interleaved ...
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Configuration Register Table 13. Burst type definition (continued) 4 words Start Sequen- Inter- Add tial leaved 0 0-1-2-3 1 1-2-3-4 2 2-3-4-5 3 3-4-5-6 ... 7 7-8-9-10 ... 12-13-14 13-14-15- 13 WAIT-16 14-15- WAIT- 14 WAIT-16- 17 15-WAIT- ...
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M58WRxxxKU, M58WRxxxKL Figure 7. X-latency and data output configuration example 1st cycle (1) A16-Amax VALID ADDRESS ADQ15-ADQ0 VALID ADDRESS 1. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in ...
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Configuration Register Figure 8. Wait configuration example (1) A16-Amax VALID ADDRESS ADQ15-ADQ0 VALID ADDRESS WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT ...
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... Asynchronous Read mode In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for Asynchronous operations. ...
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... In Synchronous Burst Read mode the data is output in bursts synchronized with the clock possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used ...
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... WAIT being gated by E remains active and will not revert to high-impedance when G goes high two or more devices are connected to the system’s READY signal, to prevent bus contention the WAIT signal of the Flash memory should not be directly connected to the system’s READY signal. ...
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... Dual operations between the Parameter Bank and either of the CFI, the OTP or the Electronic Signature memory space are not allowed. are allowed or not between the CFI, the OTP, the Electronic Signature locations and the memory array ...
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M58WRxxxKU, M58WRxxxKL Table 15. Dual operations allowed in same bank Status of Read bank Array Idle Yes (1)) Programming – Erasing – Program Yes Suspended Erase Yes Suspended 1. The Read Array command is accepted but the data output is ...
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Block locking 11 Block locking The M58WRxxxKU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows ...
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M58WRxxxKU, M58WRxxxKL 11.4 Lock-Down state Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down ...
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Block locking Table 17. Lock status Current Protection Status (WP, ADQ1, ADQ0) Current Program/Erase State Allowed 1,0,0 (2) 1,0,1 1,1,0 1,1,1 0,0,0 (2) 0,0,1 0,1,1 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ ...
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M58WRxxxKU, M58WRxxxKL 12 Program and erase times and endurance cycles The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 18 depends on the voltage supply used. Table 18. Program, erase times ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 19. ...
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M58WRxxxKU, M58WRxxxKL 14 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under ...
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DC and AC parameters Figure 10. AC measurement load circuit Table 21. Capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. 62/123 V DDQ V DD DEVICE UNDER TEST 0.1µF 0.1µ ...
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M58WRxxxKU, M58WRxxxKL Table 22. DC characteristics - currents Symbol I Input leakage current LI I Output leakage current LO Supply current Asynchronous Read (f=6 MHz) Supply current Synchronous Read (f=66 MHz) I DD1 Supply current Synchronous Read (f=86 MHz) Supply ...
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DC and AC parameters Table 23. DC characteristics - voltages Symbol V Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage program voltage-logic PP1 program ...
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M58WRxxxKU, M58WRxxxKL Figure 11. Asynchronous random access read ac waveforms DC and AC parameters 65/123 ...
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DC and AC parameters Table 24. Asynchronous Read ac characteristics Symbol Alt t t AVAV t t AVQV ACC t ELTV ( ELQV t EHTZ ( EHQX ( EHQZ ( GLQV (2) ...
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M58WRxxxKU, M58WRxxxKL Figure 12. Synchronous Burst Read ac waveforms DC and AC parameters 67/123 ...
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DC and AC parameters Figure 13. Single Synchronous Read ac waveforms 68/123 M58WRxxxKU, M58WRxxxKL ...
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M58WRxxxKU, M58WRxxxKL Figure 14. Synchronous Burst Read Suspend ac waveforms DC and AC parameters 69/123 ...
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DC and AC parameters Figure 15. Clock input ac waveform Table 25. Synchronous Read ac characteristics Symbol t t AVKH AVCLKH t t ELKH ELCLKH t ELTV t EHEL t EHTZ t GHTV t GLTV t t KHAX CLKHAX t ...
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M58WRxxxKU, M58WRxxxKL Figure 16. Write ac waveforms, Write Enable controlled DC and AC parameters 71/123 ...
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DC and AC parameters Table 26. Write ac characteristics, Write Enable controlled Symbol Alt t t AVAV WC t AVLH t t DVWH DS t ELLH t t ELWL CS t ELQV t GHLL t GHWL t LHAX t LHGL ...
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M58WRxxxKU, M58WRxxxKL Figure 17. Write ac waveforms, Chip Enable controlled DC and AC parameters 73/123 ...
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DC and AC parameters Table 27. Write ac characteristics, Chip Enable controlled Symbol Alt t t AVAV WC t AVLH t t DVEH EHDX EHEL WPH t EHLL t t EHWH ...
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M58WRxxxKU, M58WRxxxKL Figure 18. Reset and Power-up ac waveforms tVDHPH VDD, VDDQ Table 28. Reset and Power-up ac characteristics Symbol Parameter Reset Low to t PLWL Write Enable Low, t PLEL Chip Enable Low, t ...
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Package mechanical 15 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box ...
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M58WRxxxKU, M58WRxxxKL Table 29. VFBGA44 7.5 × 5 mm, 10 × 4 ball array, 0.50 mm pitch, package mechanical data Symbol Typ 0.660 b 0.300 D 7.500 D1 4.500 D2 6.500 ddd E 5.000 E1 1.500 E2 ...
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... E = ECOPACK® Package, Standard Packing U = ECOPACK® Package, Tape & Reel Packing, 16mm Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.), Daisy chain ordering information, or for further information on any aspect of this device, please contact the ST Sales Office nearest to you ...
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M58WRxxxKU, M58WRxxxKL Appendix A Block address tables Table 31. Top boot block addresses, M58WR016KU (1) Bank Size (Kword) ...
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Block address tables Table 31. Top boot block addresses, M58WR016KU (continued) (1) Bank There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main ...
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M58WRxxxKU, M58WRxxxKL Table 32. Bottom boot block addresses, M58WR016KL (continued) (1) Bank There are two Bank Regions: Bank Region 2 contains all the banks that are ...
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Block address tables Table 33. Top boot block addresses, M58WR032KU (1) Bank 82/123 M58WRxxxKU, M58WRxxxKL # Size (Kword ...
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M58WRxxxKU, M58WRxxxKL Table 33. Top boot block addresses, M58WR032KU (continued) (1) Bank 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that ...
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... Block address tables Table 34. Bottom boot block addresses, M58WR032KL (1) Bank 84/123 M58WRxxxKU, M58WRxxxKL # Size (Kword ...
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... M58WRxxxKU, M58WRxxxKL Table 34. Bottom boot block addresses, M58WR032KL (continued) (1) Bank # Size (Kword Block address tables Address range ...
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... Block address tables Table 34. Bottom boot block addresses, M58WR032KL (continued) (1) Bank 1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). ...
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M58WRxxxKU, M58WRxxxKL Table 35. Top boot block addresses, M58WR064KU (1) Bank # Size (Kword ...
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Block address tables Table 35. Top boot block addresses, M58WR064KU (continued) (1) Bank 88/123 M58WRxxxKU, M58WRxxxKL # Size (Kword ...
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M58WRxxxKU, M58WRxxxKL Table 35. Top boot block addresses, M58WR064KU (continued) (1) Bank # Size (Kword ...
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Block address tables Table 35. Top boot block addresses, M58WR064KU (continued) (1) Bank 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks ...
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M58WRxxxKU, M58WRxxxKL Table 36. Bottom boot block addresses, M58WR064KL (continued) (1) Bank # Size (Kword) 118 32 117 32 116 32 115 32 114 32 113 32 112 32 111 32 110 32 109 32 108 32 107 32 106 ...
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Block address tables Table 36. Bottom boot block addresses, M58WR064KL (continued) (1) Bank 92/123 M58WRxxxKU, M58WRxxxKL # Size (Kword ...
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M58WRxxxKU, M58WRxxxKL Table 36. Bottom boot block addresses, M58WR064KL (continued) (1) Bank # Size (Kword ...
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Block address tables Table 36. Bottom boot block addresses, M58WR064KL (continued) (1) Bank 1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks ...
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... Alternate algorithm-specific extended A query table 80h Security code area 1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 38, 39, lowest order data outputs. (1) Sub-section name Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & ...
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... Alternate vendor command set and control interface ID code second vendor - specified algorithm supported 0000h Address for alternate algorithm extended query table 0000h M58WRxxxKU, M58WRxxxKL Description M58WR016KU M58WR032KU M58WR064KU M58WR016KL M58WR032KL M58WR064KL Value ST Top Top Top Bottom Bottom Bottom "Q" "R" ...
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M58WRxxxKU, M58WRxxxKL Table 39. CFI query system interface information Offset Data 1Bh 0017h 1Ch 0020h 1Dh 0085h 1Eh 0095h 1Fh 0004h 20h 0000h 21h 000Ah 22h 0000h 23h 0003h 24h 0000h 25h 0002h 26h 0000h Description V logic supply minimum ...
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... Number of identical-size Erase block = 0007h+1 Region 1 information Block size in region 1 = 0020h * 256 byte M58WR016KL region 1 information Number of identical-size Erase blocks = 001Eh+1 M58WR032KL region 1 information Number of identical-size Erase blocks = 003Eh+1 M58WR064KL region 1 information Number of identical-size Erase blocks = 007Eh+1 Region 2 information Block size in region 2 = 0100h * 256 byte ...
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M58WRxxxKU, M58WRxxxKL Table 41. Primary algorithm-specific extended query table Offset Data (P)h = 39h 0050h 0052h Primary algorithm extended query table unique ASCII string “PRI” 0049h (P+3)h = 3Ch 0031h Major version number, ASCII (P+4)h = 3Dh 0033h Minor version ...
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... Synchronous mode read capability configuration 4 1. The variable pointer that is defined at CFI offset 15h. Table 44. Bank and Erase block region information M58WR032KU M58WR032KL Offset Data Offset (P+19)h = 52h 02h (P+19)h = 52h 1. The variable pointer that is defined at CFI offset 15h. ...
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... M58WR016KL, M58WR032KL, M58WR064KL Offset Data 01h Number of identical banks within Bank Region 1 00h Number of program or erase operations allowed in Bank Region 1: 11h Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations ...
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... The variable pointer that is defined at CFI offset 15h. 2. Applies to M58WR016KU. 3. Applies to M58WR032KU. 4. Applies to M58WR064KU. 5. Bank Regions. There are two Bank Regions, see Tables 31, 32, 33, 34, 102/123 (1) M58WR016KL, M58WR032KL, M58WR064KL Offset Data 06h Bank Region 1 Erase Block Type 2 Information 00h Bits 0-15: n+1 = number of identical-sized erase ...
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... M58WRxxxKU, M58WRxxxKL Table 46. Bank and Erase block region 2 information M58WR016KU, M58WR016KL, M58WR032KU, M58WR032KL, M58WR064KU M58WR064KL Offset Data Offset (P+28)h = 61h 01h (P+30)h = 69h (P+29)h = 62h 00h (P+31)h = 6Ah (P+2A)h = 63h 11h (P+32)h = 6Bh (P+2B)h = 64h 00h (P+33)h = 6Ch (P+2C)h = 65h 00h (P+34)h = 6Dh (P+2D)h = 66h 02h (P+35)h = 6Eh (P+2E)h = 67h 06h (P+36)h = 6Fh (P+2F)h = 68h 00h ...
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... The variable pointer that is defined at CFI offset 15h. 2. Applies to M58WR016KL. 3. Applies to M58WR032KL. 4. Applies to M58WR064KL. 5. Bank Regions. There are two Bank Regions, see Tables 31, 32, 33, 34, 104/123 (1) (continued) Description Data Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n× ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 ...
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... Any address within the bank can equally be used. 106/123 double_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (addressToProgram1, 0x35); writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; /*Memory enters read status state after the Program command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 Invalid if (status_register.SR3==1) /*V PP invalid error */ Error (1, 2) error_handler ( ) ...
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... Any address within the bank can equally be used. quadruple_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (addressToProgram1, 0x56); writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; writeToFlash (addressToProgram3, dataToProgram3) ; writeToFlash (addressToProgram4, dataToProgram4) ; /*Memory enters read status state after the Program command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 Invalid if (status_register.SR3==1) /*V PP invalid error */ Error (1, 2) error_handler ( ) ...
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Flowcharts and pseudocodes Figure 23. Program Suspend & Resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR2 = 1 YES Write FFh Read data from another address Write D0h (1) ...
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... Any address within the bank can equally be used. 3. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L. erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; writeToFlash (blockToErase, 0xD0 only ADQ12-ADQ15 and A16-Amax /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase must be toggled*/ } while (status_register.SR7 ...
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Flowcharts and pseudocodes Figure 25. Erase Suspend & Resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR6 = 1 YES Write FFh Read data from another block, Program, Set Configuration ...
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M58WRxxxKU, M58WRxxxKL Figure 26. Locking operations flowchart and pseudocode Start Write 60h (1) Write 01h, D0h or 2Fh Write 90h (1) Read Block Lock States Locking change confirmed? YES Write FFh (1) End 1. Any address within the bank can ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 112/123 protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (addressToProgram must be toggled*/ } while (status_register.SR7 ...
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M58WRxxxKU, M58WRxxxKL Figure 28. Enhanced Factory Program flowchart SETUP PHASE NO Check SR4, SR3 and SR1 for program, V and Lock Errors PP Exit PROGRAM PHASE Address Block WA1 1. Address can remain Starting Address WA1 or be incremented. Start ...
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Flowcharts and pseudocodes 16.1 Enhanced Factory Program pseudocode efp_command(addressFlow,dataFlow, the number of data to be programmed */ { /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); ...
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M58WRxxxKU, M58WRxxxKL Figure 29. Quadruple enhanced factory program flowchart SETUP PHASE Start Write 75h Address WA1 FIRST LOAD PHASE Write PD1 Address WA1 Read Status Register NO SR7 = 0? YES Check SR4, SR3 and SR1 for program, PROGRAM AND ...
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Flowcharts and pseudocodes 16.2 Quadruple enhanced factory program pseudocode quad_efp_command(addressFlow,dataFlow, the number of pages to be programmed.*/ { /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the ...
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M58WRxxxKU, M58WRxxxKL Appendix D Command interface state tables Table 47. Command interface states - modify table, next state Current CI State Read WP (2) Array setup (10/40h) (FFh) Program Ready Ready Setup Lock/CR Setup Setup Busy OTP Busy OTP IS ...
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Command interface state tables Table 47. Command interface states - modify table, next state Current CI State Read WP (2) Array setup (10/40h) (FFh) Setup EFP Busy Verify Setup Quad EFP Busy Command Interface Configuration ...
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M58WRxxxKU, M58WRxxxKL Table 48. Command interface states - Modify table, next output Current CI State Read DWP, QWP (3) (4)(5) Array Setup (FFh) (35h, 56h) Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend EFP Setup EFP Busy ...
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Command interface state tables Table 49. Command interface states - Lock table, next state Current CI State Lock/CR Setup (60h) Ready Lock/CR Setup Lock/CR Setup Ready (Lock error) Setup OTP Busy IS in OTP busy IS in OTP busy Setup ...
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M58WRxxxKU, M58WRxxxKL Table 50. Command interface states - Lock table, next output Current CI State Lock/CR OTP Setup (2) Setup (60h) Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP ...
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... Initial release. M58WR032KU/L (revision 0.2 of 21-Jul-2006) and M58WR064KU/L (revision 0.1 of 21-Sep-2006) datasheets merged. M58WR016KU and M58WR016KL part numbers added. Changes made: Document status promoted from Target Specification to Preliminary Data speed class and 86 MHz frequency added. During Erase Suspend, the Set Configuration Register command is also ...
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... M58WRxxxKU, M58WRxxxKL Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...