tc58dvm92a3ta00

Manufacturer Part Numbertc58dvm92a3ta00
Description512-mbit 64 M ? 8 Bits Cmos Nand E Prom
ManufacturerTOSHIBA Semiconductor CORPORATION
tc58dvm92a3ta00 datasheet
 


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TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64 M × 8 BITS) CMOS NAND E
DESCRIPTION
The device is a single 3.3 V 512-Mbit (553,648,128 bits) NAND Electrically Erasable and Programmable
2
PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte
Read-Only Memory (NAND E
static register which allows program and read data to be transferred between the register and the memory cell
array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes:
528 bytes × 32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array 528 × 128K × 8
Register
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
Modes
Read, Reset, Auto Page Program,
Auto Block Erase, Status Read,
Mode control
Serial input/output
Command control
PIN ASSIGNMENT
(TOP VIEW)
NC
1
NC
2
NC
3
NC
4
NC
5
NC
6
7
RY
/
BY
RE
8
CE
9
NC
10
NC
11
V
12
CC
V
13
SS
NC
14
NC
15
CLE
16
ALE
17
WE
18
WP
19
NC
20
NC
21
NC
22
NC
23
NC
24
2
PROM
Power supply
Access time
Cell array to register 30 µs max
Serial Read Cycle
Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
Package
TSOP I 48-P-1220-0.50 (Weight: 0.53g typ.)
PIN NAMES
48
NC
I/O1 to I/O8
I/O port
47
NC
46
NC
CE
Chip enable
45
NC
44
I/O8
WE
Write enable
43
I/O7
42
I/O6
RE
Read enable
41
I/O5
40
NC
CLE
Command latch enable
39
NC
ALE
Address latch enable
38
NC
37
V
CC
WP
Write protect
36
V
SS
35
NC
RY
/
BY
Ready/Busy
34
NC
33
NC
V
Power supply
32
I/O4
CC
31
I/O3
V
Ground
30
I/O2
SS
29
I/O1
28
NC
27
NC
26
NC
25
NC
1
TC58DVM92A3TA00
= 2.7 V to 3.6 V
V
CC
50 ns min
30 mA max
30 mA max
30 mA max
50 µA max
2008-12-10

tc58dvm92a3ta00 Summary of contents

  • Page 1

    ... NC ALE Address latch enable Write protect Ready/Busy Power supply 32 I/ I/O3 V Ground TC58DVM92A3TA00 = 2 3 min 30 mA max 30 mA max 30 mA max 50 µA max 2008-12-10 ...

  • Page 2

    ... Operating Temperature opr *(Ta = 25° MHz) CAPACITANCE SYMB0L PARAMETER C Input IN C Output OUT This parameter is periodically sampled and is not tested for every device. * TC58DVM92A3TA00 Status register Address register Command register Control HV generator VALUE − 0.6 to 4.6 − 0.6 to 4.6 − ≤ 4 0.3 260 − ...

  • Page 3

    ... − − 400 µ 2 0.4 V pin TC58DVM92A3TA00 TYP. MAX UNIT ⎯ 4096 Blocks TYP. MAX UNIT ⎯ 3.6 V ⎯ ⎯ × 0. MIN TYP. MAX UNIT ⎯ ...

  • Page 4

    ... WE High to Busy WB t ALE Low to RE Low (Read Cycle) AR2 t RE Last Clock Rising Edge to Busy (in Sequential Read High to Ready (When interrupted Read Mode) CRY t Device Reset Time (Ready/Read/Program/Erase) RST TC58DVM92A3TA00 MIN MAX ⎯ 0 ⎯ 10 ⎯ 0 ⎯ 10 ⎯ 25 ⎯ ...

  • Page 5

    ... If the delay is less than CEH ≥ 100 ns t CEH : → Busy signal is not output. A 527 A Busy t CRY MIN TYP. MAX ⎯ 300 700 ⎯ ⎯ ⎯ TC58DVM92A3TA00 * : UNIT NOTES µ s ⎯ 2008-12-10 ...

  • Page 6

    ... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE CE RE Setup Time WE I/O Command Input Cycle Timing Diagram CLE t CLS ALS ALE t DS I/O Hold Time CLH ALH TC58DVM92A3TA00 : 2008-12-10 ...

  • Page 7

    ... A16 A17 to A24 TC58DVM92A3TA00 ALH A25 : CLH 527 2008-12-10 ...

  • Page 8

    ... REH RHZ REA RHZ t CLS WHC CEA t WHR TC58DVM92A3TA00 CHZ REA RHZ t CEA t CHZ REA RHZ Status output : 2008-12-10 ...

  • Page 9

    ... ALH AR2 REA A17 D D OUT A25 A24 N 9 TC58DVM92A3TA00 t CEH t CRY OUT OUT OUT 527 CHZ RC t RHZ OUT OUT ...

  • Page 10

    ... Read operation using 50h command ALH A17 A25 to A16 to A24 t ALH A17 A25 to A16 to A24 10 TC58DVM92A3TA00 t AR2 REA OUT OUT OUT 256 + N 256 + 527 : AR2 ...

  • Page 11

    ... N to A24 Page t R address M Page M access A17 to A25 A25 A24 Page t 256 + 256 + 256 + R address Page M access 11 TC58DVM92A3TA00 527 527 t R Page access : 527 527 t R Page access : 2008-12-10 ...

  • Page 12

    ... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/ 50h I/O8 A16 Column address A17 to A25 A25 A24 Page t 512 + 512 + 512 + R address Page M access 12 TC58DVM92A3TA00 527 512 513 514 527 t R Page access : 2008-12-10 ...

  • Page 13

    ... Do not input data while data is being output ALH WB BERASE D0h Erase Start Busy command : not input data while data is being output TC58DVM92A3TA00 t PROG 10h 70h Status output Status 70h output Status Read command 2008-12-10 ...

  • Page 14

    ... ID Read Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O 90h 00h Address input CEA t t ALH ALEA t REA t REA 98h Device code Maker code 14 TC58DVM92A3TA00 76h : 2008-12-10 ...

  • Page 15

    ... H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vcc with an appropriate resister. = L), such as during a Program or Erase or Read operation, and after the falling edge REA 15 TC58DVM92A3TA00 signal is in 2008-12-10 ...

  • Page 16

    ... An address is read in via the I/O port over four 8 I/O consecutive clock cycles, as shown in Table 1. I/O6 I/O5 I/O4 I/O3 I/O2 I/ A14 A13 A12 A11 A10 A9 A22 A21 A20 A19 A18 A17 * A25 16 TC58DVM92A3TA00 A0 to A7: Column address A9 to A25: Page address A14 to A25: Block address A9 to A13: NAND address in block 2008-12-10 ...

  • Page 17

    ... ALE L), such as during a Program or Erase or Read operation, CE input goes High. ALE TC58DVM92A3TA00 * V/V CC I/O1 to I/O8 Power Data output Active High impedance Active 2008-12-10 ...

  • Page 18

    ... Read Mode (3) 50 Reset FF Auto Program 10 Auto Block Erase 60 Status Read 70 ID Read 90 Acceptable while Busy HEX data bit assignment ⎯ (Example) ⎯ ⎯ ⎯ 1 ⎯ I/O8 7 ⎯ D0 ⎯ ⎯ 18 TC58DVM92A3TA00 Serial data input: 80h I/O1 2008-12-10 ...

  • Page 19

    ... Busy 527 The operation of the device after input of the 01h command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). Cell array 19 TC58DVM92A3TA00 2008-12-10 ...

  • Page 20

    ... address. (An 00h or an 01h command is necessary to move the pointer back to the 0 to 511 main memory cell location.) Data output Busy Busy (01h) 527 A Sequential Read (2) 20 TC58DVM92A3TA00 Data output t R Busy (50h) 512 527 A Sequential Read (3) 2008-12-10 ...

  • Page 21

    ... Not Protected Device 2 3 Busy 70h Status on Device 1 Status on Device N pin signals from multiple devices are wired together as shown in the BY 21 TC58DVM92A3TA00 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device 2008-12-10 ...

  • Page 22

    ... If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Status Read command Busy 22 TC58DVM92A3TA00 Pass 70 I/O Fail automatically returns to Ready after Pass 70 ...

  • Page 23

    ... RST FF t RST FF (max 7 µ RST command is invalid, but the third 23 TC58DVM92A3TA00 Figure 7. 00 Figure 8. 00 (max 500 µ s) Figure 9. 00 Figure 10. I/O status: Pass/Fail → Pass Ready/Busy → Ready I/O status: Ready/Busy → Busy Figure 11. (2) ( command is valid ...

  • Page 24

    ... Address 00h Table 6. ID Codes read out by ID read command 90h I/O8 I/O7 Maker code 1 0 Device code CEA t ALEA t REA 98h Maker code Figure 12. ID Read timing I/O6 I/O5 I/O4 I/O3 I/ TC58DVM92A3TA00 76h Device code I/O1 Hex Data 0 98h 0 76h 2008-12-10 ...

  • Page 25

    ... V and CE signal is kept high Operation Figure 13. Power-on/off Sequence becomes 2.5V, it should begin access after about 1 ms Reset Figure 14. For this operation the “FFh” command is needed. Programming cannot be executed. 25 TC58DVM92A3TA00 Don’t care V IL 2008-12-10 ...

  • Page 26

    ... Read mode. In this case, data output starts automatically from address N and address input is unnecessary. Ex.) Random page program (Prohibition) DATA IN: Data (1) Page 0 Page 1 Page 2 Page 15 Page 31 Figure 15. page programming within a block 70 Status Read command input Figure 16. 26 TC58DVM92A3TA00 Data (32) Data register (2) (16) (3) (1) (32) 00 [A] Status Read Status output 2008-12-10 ...

  • Page 27

    ... Add Start point A area 10h Add DIN Start point C Area 10h Add DIN Start point B Area Figure 18. Example of How to Set the Pointer 27 TC58DVM92A3TA00 255 256 511 512 527 B C Pointer control Figure 17 Pointer control 50h Add Start point C area 00h Add ...

  • Page 28

    ... Ready 1.5 µ s 1.0 µ 0.5 µ Ω 28 TC58DVM92A3TA00 / BY buffer consists of an open drain Busy 3 25° 100 Ω Ω Ω ...

  • Page 29

    ... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE 80 DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE 60 DIN (100 ns min) WW TC58DVM92A3TA00 2008-12-10 ...

  • Page 30

    ... Although the device may read in a fifth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00h, 01h or 50h Internal read operation starts when WE goes High in the fourth cycle. Program operation CLE CE WE ALE I/O 80h TC58DVM92A3TA00 Address input Figure 20. Address input Ignored Figure 21. 30 Ignored Data input 2008-12-10 ...

  • Page 31

    ... Busy state. (Refer to Figure 23.) I/O 00h/01h/50h Hence the RE clock input must start after the address input. All 1 s All 1 s Data Pattern 2 All 1 s Data Pattern 2 Figure 22 Address input Figure 23. 31 TC58DVM92A3TA00 Data Pattern 3 Data Pattern 3 2008-12-10 ...

  • Page 32

    ... Read Check: Read column 517 of the 1st page Start Block Fail Read Check Pass Bad Block * 1 Block No. = 4096 Yes End Figure 25 32 TC58DVM92A3TA00 TYP. MAX UNIT ⎯ 4096 Block in the block. If the column is not FFh, define the block as a bad block. 2008-12-10 ...

  • Page 33

    ... Status Read after Program → Block Replacement ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 26. 33 TC58DVM92A3TA00 2008-12-10 ...

  • Page 34

    ... Package Dimensions Weight: 0.53 g (typ.) TC58DVM92A3TA00 34 2008-12-10 ...

  • Page 35

    ... Revision History Date Rev. Description 2008-07-25 1.00 Original version 2008-10-10 1.10 Changed the description of I TC58DVM92A3TA00 CCS 35 2008-12-10 ...

  • Page 36

    ... Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. • The products described in this document are subject to foreign exchange and foreign trade control laws. TC58DVM92A3TA00 The 36 information 2008-12-10 ...