tza3054a NXP Semiconductors, tza3054a Datasheet - Page 12

• Manufacturer Part Number: tza3054a
• Description: 100 Mbits/s To 3.2 Gbits/s A-rate Tm Limiting Amplifier
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13466
Objective data sheet
8.5.4 Power-up
8.5.5 Default at power-up
8.5.6 Interrupt controller
8.5.7 I
At power-up an internal safe condition signal is generated once the V
sufficiently high for proper operation and the internal reference voltage has settled. This
signal is used to generate a Power-On-Reset (POR) signal that resets all internal circuits
to their default value.
All I
The TZA3054A features an interrupt controller, based on status flags. These flags are:
The controller contains two I
(INTERRUPT at address 00h) and the I
The I
shows the present state of the receiver.
The I
read action of the I
is still present, the flag is immediately reset in the I
status register is not reset since it always shows the present state of the TZA3054A.
The chip can be configured by using the I
The I
A detailed list of all I
Section
During power-up, all I
Table
Table 3:
A6
1
2
•
•
•
•
•
•
•
•
•
•
C-bus
2
DC offset compensation: on
Automatic bandwidth adjustment (ACE on)
Automatic slew rate adjustment (ACE on)
Pin adjustable / selectable LOSTH, JAM and LVL
LOS hysteresis 3 dB
LOS output open drain (active LOW)
JAM active LOW.
Loss of signal
Temperature alarm (> 125 C with a hysteresis of approximately 4 C)
Supply voltage alarm (< 2.85 V with a hysteresis of approximately 50 mV).
C-bus registers are reset to their default setting at power-up, which are:
2
2
2
3.
C-bus interrupt register stores the history, while the I
C-bus interrupt and status registers can be polled by an I
C-bus address of the TZA3054A is D2h for writing and D3h for reading.
8.7.
I
2
A5
1
C-bus address of TZA3054A
2
C-bus interrupt register clears all interrupt flags. If the alarm condition
2
C-bus registers and an explanation of their contents is given in
2
Rev. 01 — 12 August 2004
C-bus registers are reset to their default value as indicated in
A4
0
2
C-bus registers, namely the I
A3
1
100 Mbit/s to 3.2 Gbit/s A-rate
2
C-bus status register (STATUS at address 01h).
2
C-bus connections SDA and SCL.
A2
0
2
C-bus interrupt register. The I
A1
0
2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2
C-bus interrupt register
C-bus status register always
2
C-bus read action. The
TZA3054A
A0
1
CC
limiting amplifier
voltage is
R/W
X
2
C-bus
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