ssl1750 NXP Semiconductors, ssl1750 Datasheet - Page 9

• Manufacturer Part Number: ssl1750
• Description: Smps Control Ic For Led Drivers
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SSL1750_1
Product data sheet
7.1.4 Fast latch reset
7.1.5 Overtemperature protection (OTP)
7.2.1 t
7.2.2 Valley switching and demagnetization (pin PFCAUX)
7.2 Power factor correction circuit
In a typical application, the mains can be interrupted briefly to reset the latched protection.
The PFC bus capacitor, C
reset.
Typically, the PFC bus capacitor, C
level. When the latched protection is set, the clamping circuit of the VINSENSE circuit is
disabled (see also
750 mV (typ) and is then raised to 870 mV (typ), the latched protection is reset.
The latched protection will also be reset by removing both the voltage on pin V
pin HV.
An accurate internal temperature protection is provided in the circuit. When the junction
temperature exceeds the thermal shutdown temperature, the IC only stops switching. As
long as OTP is active, the V
circuit is supplied from pin HV if the V
OTP is a latched protection. It can be reset by removing both the voltage on pin V
on pin HV or by the fast latch reset function, see
The power factor correction circuit operates in quasi-resonant or discontinuous conduction
mode with valley switching. The next primary stroke is only started when the previous
secondary stroke has ended and the voltage across the PFC MOSFET has reached a
minimum value. The voltage on pin PFCAUX is used to detect transformer
demagnetization and the minimum voltage across the external PFC MOSFET switch.
The power factor correction circuit is operated in t
reduction of a typical application is well within the class-D requirements.
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry
connected to pin PFCAUX detects the end of the secondary stroke. It also detects the
voltage across the PFC MOSFET. The next stroke is started if the voltage across the PFC
MOSFET is at its minimum in order to reduce switching losses and ElectroMagnetic
Interference (EMI) (valley switching).
If no demagnetization signal is detected on pin PFCAUX, the controller generates a Zero
Current Signal (ZCS), 50 s (typ) after the last PFC gate signal.
If no valley signal is detected on pin PFCAUX, the controller generates a valley signal
4 s (typ) after demagnetization was detected.
To protect the internal circuitry, for example during lightning events, it is advisable to add a
5 k series resistor to this pin. To prevent incorrect switching due to external disturbance,
the resistor should be placed close to the IC on the printed-circuit board.
on
control
Section
Rev. 01 — 15 September 2008
bus
7.2.8). As soon as the VINSENSE voltage drops below
CC
, does not have to discharge for this latched protection to
capacitor is not recharged from the HV mains. The OTP
bus
, has to discharge for the V
CC
supply voltage is not sufficient.
Section
on
control. The resulting mains harmonic
SMPS control IC for LED drivers
7.1.4.
CC
to drop to this reset
SSL1750
© NXP B.V. 2008. All rights reserved.
CC
and on
CC
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and