uaa2062 NXP Semiconductors, uaa2062 Datasheet - Page 12

• Manufacturer Part Number: uaa2062
• Description: Analog Cordless Telephone Ic
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Other features
PLL
Pin V
RX and TX PLLs. It is regulated at 3 V. Pin V
provides the supply voltage input for the internal voltage
regulator. Two capacitors of 47 F and 100 nF must be
connected to pin V
regulated voltage. The tolerance of the regulated voltage
is initially 8% but is improved to 4% after the internal
band gap voltage reference is adjusted via the
microcontroller.
The voltage regulator is always turned on. In the inactive
mode the calibration is turned off to reduce current
consumption. In this mode, the V
300 A to the microcontroller. The output drive capability
is 3 mA. The voltage regulator is able to supply the
microcontroller.
The local oscillator LO2 and the RX and TX phase
detectors are powered by the internal voltage regulator at
pin V
level for most I/O pins (LO2I and LO2O) equals the
regulated voltage at pin V
L
The low-battery detector measures the voltage level of the
V
input of the comparator is connected to VB, the other to the
middle point of the resistance divider.
2000 Aug 10
handbook, full pagewidth
OW
CC(AU)
Analog cordless telephone IC
-
VOLTAGE REGULATOR
BATTERY DETECTOR
ref(PLL)
DATA
ref(PLL)
CLK
EN
using a resistance divider and a comparator. One
. Therefore, the maximum input and output
provides the internal supply voltage for the
50%
50%
ref(PLL)
D14
t HD;EC
to filter and stabilize this
ref(PLL)
t SU;CE
.
50%
ref(PLL)
data bits (15)
t SU;DC
Fig.10 Digital signals timing requirement.
block supplies
D13
CC(AU)
12
The comparator has a built-in hysteresis to prevent
spurious switching. The precision of the detection depends
on the divider accuracy, the comparator offset and the
accuracy of the reference voltage VB. The output is
multiplexed at pin CDBDO. When the battery voltage level
is below the threshold voltage the output CDBDO is going
LOW.
Microcontroller serial interface
Pins DATA, CLK and EN provide a 3-wire unidirectional
serial interface for programming the reference counters,
the transmit and receive channel divider counters and the
control functions.
The interface consists of 18-bit shift registers connected to
a matrix of registers organized as 6 words of 18 bits. The
leading 15 bits include the data D14 to D0. The trailing
3 bits set up the address AD2 to AD0. The data is entered
with the most significant bit D14 first. The last bit is
bit AD0.
Pins DATA and CLK are used to load data into the shift
register. Figure 10 shows the timing required on all pins.
Data is clocked into the shift registers on negative clock
transitions.
The serial interface pins DATA, CLK and EN, are supplied
by V
pins which allow the logic and registers to be internally
powered by V
The ESD protection diodes on these pins are connected to
V
open-collector outputs.
D12
CC(AU)
ref(PLL)
. All the digital outputs (CDBDO and DATO) are
. Internal level shifters are provided after the
AD1
CC(AU)
address bits (3)
.
AD0
data bits latched
t END
Product specification
UAA2062
t w
MGR004