W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 153

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

CRF2 (Default 0x00)
Watching Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to
load the value to Watching Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any
Mouse Interrupt or Keyboard Interrupt happen will also cause to reload the non-zero value to
Watching Dog Counter and count down. Read this register can not access Watching Dog Timer
Time-out value, but can access the current value in Watching Dog Counter.
CRF3 (WDT_CTRL0, Default 0x00)
CRF4 (WDT_CTRL1, Default 0x00)
*Note : 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
Bit 7-0 :
Watching Dog Timer Control Register #0
Bit 7-4 : Reserved
Bit 3 : When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output.
Bit 2 : Mouse interrupt reset Enable or Disable
Bit 1 : Keyboard interrupt reset Enable or Disable
Bit 0 : Reserved.
Watching Dog Timer Control Register #1
Bit 7-4 : Reserved
Bit 3 : Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
Bit 2 : Force Watching Dog Timer Time-out, Write only*
Bit 1 : Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W
Bit 0 : Watching Dog Timer Status, R/W
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then
= 0x00 Time-out Disable
= 0x01 Time-out occurs after 1 minute
= 0x02 Time-out occurs after 2 minutes
= 0x03 Time-out occurs after 3 minutes
................................................
= 0xFF Time-out occurs after 255 minutes
= 1 Enable
= 0 Disable
= 1 Watching Dog Timer is reset upon a Mouse interrupt
= 0 Watching Dog Timer is not affected by Mouse interrupt
= 1 Watching Dog Timer is reset upon a Keyboard interrupt
= 0 Watching Dog Timer is not affected by Keyboard interrupt
= 1 Enable
= 0 Disable
= 1 Force Watching Dog Timer time-out event; this bit is self-clearing.
= 1 Enable
= 0 Disable
= 1 Watching Dog Timer time-out occurred.
= 0 Watching Dog Timer counting
connect to set the Bit 0(Watching Dog Timer Status). The ORed signal is self-clearing.
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W83977F/ W83977AF
Publication Release Date: March 1998
PRELIMINARY
Revision 0.58