W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 55

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W83977AF

Manufacturer Part Number
W83977AF
Description
W83877TF Plus Kbc, Cir, RTC
Manufacturer
Information Storage Devices, Inc
Datasheet
BDLAB = 0
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
Register Address Base
+ 0
+ 0
+ 1
+ 2
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
+ 1
TABLE 3-1 UART Register Bit Map
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Baudrate Divisor
Interrupt Control
Interrupt Status
Status Register
Buffer Register
UART Control
UART Status
User Defined
Divisor Latch
(Read Only)
(Write Only)
(Read Only)
UART FIFO
(Write Only)
Transmitter
Handshake
Handshake
Latch Low
Receiver
Register
Register
Register
Register
Register
Register
Register
Register
Baudrate
Control
Control
Buffer
High
RBR
UCR
HCR
USR
HSR
UDR
TBR
UFR
BHL
ICR
ISR
BLL
RBR Data
RBR Data
RX Data
TX Data
(ERDRI)
Terminal
Toggling
Interrupt
Interrupt
Pending
(TCTS)
(DLS0)
Enable
Enable
Length
(RDR)
Ready
Ready
(DTR)
Ready
Select
FIFO
"0" if
Data
Data
CTS
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
0
(ETBREI)
RX Data
Toggling
TX Data
Interrupt
Interrupt
Request
Overrun
(TDSR)
(DLS1)
Enable
Length
RCVR
(OER)
Empty
Status
Select
(RTS)
Bit (0)
Reset
FIFO
Send
Error
DSR
Bit 1
Bit 1
TBR
Data
Bit 1
Bit 1
Bit 1
Bit 9
to
1
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
(EUSRI)
Interrupt
TX Data
(MSBE)
(PBER)
Interrupt
Multiple
Enable
Enable
(FERI)
Status
Bit (1)
Reset
Bit 10
XMIT
FIFO
Input
Error
Edge
Bit 2
Bit 2
Bit 2
Bit 2
USR
RI
2
Bit Number
Toggling
RX Data
Interrupt
(EHSRI)
Interrupt
TX Data
No Stop
(NSER)
(TDCD)
Bit (2)**
W83977F/ W83977AF
Enable
Enable
Enable
Status
Select
(PBE)
Parity
Bit 11
Mode
HSR
DMA
Error
DCD
Bit 3
Bit 3
Bit 3
Bit 3
IRQ
Bit
Bit
3
Publication Release Date: January 1997
Loopback
Reserved
Detected
RX Data
TX Data
to Send
Internal
Enable
Enable
(EPE)
(SBD)
(CTS)
Parity
Silent
Bit 12
Clear
Even
Bit 4
Bit 4
Bit 4
Bit 4
Byte
4
0
0
PRELIMINARY
Reversed
RX Data
TX Data
Bit Fixed
Data Set
-44 -
(TBRE)
Enable
PBFE)
(DSR)
Empty
Ready
Bit 13
Parity
Bit 5
Bit 5
TBR
Bit 5
Bit 5
5
0
0
0
Revision 0.50
Active Level
RX Data
Interrupt
Indicator
TX Data
Enabled
(TSRE)
Silence
Enable
FIFOs
Empty
(SSE)
(LSB)
Bit 14
TSR
Ring
Bit 6
Bit 6
Bit 6
Bit 6
(RI)
Set
RX
**
6
0
0
Data Carrier
Active Level
Access Bit
Indication
RX Data
(BDLAB)
(RFEI) **
Baudrate
RX FIFO
Interrupt
TX Data
Enabled
Divisor
FIFOs
(MSB)
Detect
(DCD)
Bit 15
Latch
Error
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0

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