W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 72

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

Legacy IR Register:
This is a temporary register that can be accessed and defined by the user.
Advanced IR Register:
Bit 7
Bit 6
Bit 5
Bit 4:
Bit 3
Bit 2:
Bit 1:
Bit 0:
4.3 Set1 - Legacy Baud Rate Divisor Register
Address Offset Register Name
0
1
2
3
4
5
6
7
MIR, FIR Modes:
MIR, FIR Modes:
MIR, FIR Modes:
Remote IR mode:
MIR, FIR modes:
Remote IR Modes:
MIR, FIR Modes:
MIR, FIR Modes:
MIR, FIR, Remote IR Modes:
FLC_ACT - Flow Control Active
Set to 1 when the flow control occurs. Cleared to 0 when this register is read. Note that
this will be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR
mode or MIR/FIR mode operated in DMA function switches to SIR mode.
UNDRN - Underrun
Set to 1 when transmitter is empty and S_FEND (bit 3 of this register) is not set in PIO
mode or no TC (Terminal Count) in DMA mode. Cleared to 0 after a write to 1.
RX_BSY - Receiver Busy
Set to 1 when receiver is busy or active in process.
RX_IP - Receiver in Process
Set to 1 when receiver is in process.
LST_FE - Lost Frame End
Set to 1 when a frame end in a entire frame is lost. Cleared to 0 when this register is
read.
RX_PD - Receiver Pulse Detected
Set to 1 when one or more remote pulses are detected. Cleared to 0 when this register is
read.
S_FEND - Set a Frame End
Set to 1 when trying to terminate the frame, that is, the procedure of PIO command is
An Entire Frame = Write Frame Data (First) + Write S_FEND (Last)
This bit should be set to 1, if use in PIO mode, to avoid transmitter underrun. Note that
setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this
bit should be set to 0 in DMA mode.
Reserved.
LB_SF - Last Byte Stay in FIFO
A 1 in this bit indicates one or more frame ends still stay in receiver FIFO.
RX_TO - Receiver FIFO or Frame Status FIFO time-out
Set to 1 when receiver FIFO or frame status FIFO time-out occurs
UDR/ESCR
UCR/SSR
ISR/UFR
HCR
USR
HSR
BHL
BLL
Baud Rate Divisor Latch (Low Byte)
Baud Rate Divisor Latch (High Byte)
Interrupt Status or IR FIFO Control Register
IR Control or Sets Select Register
Handshake Control Register
IR Status Register
Handshake Status Register
User Defined Register
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Register Description
W83977F/ W83977AF
Publication Release Date: March 1998
PRELIMINARY
Revision 0.58