W83977A Winbond Electronics Corp America, W83977A Datasheet - Page 125

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W83977A

Manufacturer Part Number
W83977A
Description
Winbond I/O
Manufacturer
Winbond Electronics Corp America
Datasheet

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CRF4 (WDT_CTRL1, Default 0x00)
*Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
11.9 Logical Device 9 (GP I/O Port III)
CR30 (Default 0x00)
CR60, CR 61 (Default 0x00, 0x00)
CR62, CR 63 (Default 0x00, 0x00)
CR64, CR 65 (Default 0x00, 0x00)
CR70 (Default 0x00)
CR72 (Default 0x00)
Watch Dog
Bit 7 - 4: Reserved
Bit 3: Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
Bit 2: Force
Bit 1: Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W
Bit 0:
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
These two registers select GP3 I/O base address [0x100:0xFFF] on 1 byte boundary.
These two registers select GP32 alternate function Primary I/O base address [0x100:0xFFE] on 2-
byte boundary; They are available as you setting GP32 to be an alternate function (General
Purpose Address Decode).
These two registers select GP33 alternate function Primary I/O base address [0x100:0xFFF] on 2-
byte boundary; They are available as you setting GP33 to be an alternate function (General
Purpose Address Decode).
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for GP30 as you setting GP30 to be an alternate function
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for GP31 as you setting GP31 to be an alternate function
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then
Watch Dog
= 1 Enable
= 0 Disable
= 1 Force
= 1 Enable
= 0 Disable
= 1
= 0
connect to set the Bit
= 0 Logical device is inactive.
(Interrupt Steering).
(Interrupt Steering).
Watch Dog
Watch Dog
Timer Control Register #1
Watch Dog
Watch Dog
Timer Status, R/W
Timer time-out occurred.
Timer counting
0(Watch Dog
Timer Time-out, Write only*
Timer time-out event; this bit is self-clearing.
Timer Status). The ORed signal is self-clearing.
-114-
Publication Release Date: March 1998
W83977TF
PRELIMINARY
Revision 0.62

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