t89c51rd2-slscl ATMEL Corporation, t89c51rd2-slscl Datasheet - Page 33

• Manufacturer Part Number: t89c51rd2-slscl
• Description: 0 To 40 Mhz Flash Programmable 8-bit Microcontroller
• Manufacturer: ATMEL Corporation

Serial I/O Port
Framing Error Detection
4243G–8051–05/03
The serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-
taneously and at different baud rates
Serial I/O port includes the following enhancements:
•
•
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-
ter (See Figure 13).
Figure 13. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 20.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 14. and Figure 15.).
Figure 14. UART Timings in Mode 1
Framing error detection
Automatic address recognition
SMOD0=X
SMOD0=1
RXD
SM0/FE
SMOD1
FE
RI
SMOD0
SM1
Start
bit
SM2
D0
-
D1
REN
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD0 = 0)
POF
To UART framing error control
D2
TB8
GF1
D3
Data byte
RB8
GF0
D4
PD
D5
TI
D6
IDL
RI
D7
T89C51RD2
SCON (98h)
PCON (87h)
Stop
bit
33