t89c51rd2-slscl ATMEL Corporation, t89c51rd2-slscl Datasheet - Page 46

• Manufacturer Part Number: t89c51rd2-slscl
• Description: 0 To 40 Mhz Flash Programmable 8-bit Microcontroller
• Manufacturer: ATMEL Corporation

Hardware Watchdog
Timer
Using the WDT
46
T89C51RD2
The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x T
make the best use of the WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2
capability, ranking from 16ms to 2s @ F
WDTPRG register description, Table 29. (SFR0A7h).
Table 28. WDTRST Register
WDTRST Address (0A6h)
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
Table 29. WDTPRG Register
WDTPRG Address (0A7h)
Reset value
Number
Bit
T4
7
6
5
4
3
2
1
7
Mnemonic
Bit
T4
T3
T2
T1
T0
S2
S1
T3
6
X
7
Description
Reserved
The value read from this bit is undeterminated. Do not try to set this bit..
WDT Time-out select bit 2
WDT Time-out select bit 1
T2
5
X
6
7
X
5
T1
4
counter has been added to extend the Time-out
OSC
= 12MHz. To manage this feature, refer to
X
4
T0
3
OSC
X
3
S2
, where T
2
OSC
2
X
S1
1
= 1/F
4243G–8051–05/03
OSC
S0
X
1
0
. To