at91sam9g35-cu ATMEL Corporation, at91sam9g35-cu Datasheet - Page 11

• Manufacturer Part Number: at91sam9g35-cu
• Description: At91sam Arm-based Embedded Mpu
• Manufacturer: ATMEL Corporation

Table 4-3.
4.3
11053AS–ATARM–27-Jul-11
Ball
N4
R1
R4
R3
U3
U1
U2
U4
R5
U5
U6
R6
U7
R7
U8
R9
R8
U9
D3
D4
L3
P1
L4
T3
P4
T1
T2
T4
P5
T5
T6
T7
T8
P8
217-ball BGA Package Pinout
Power Rail
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDANA
VDDANA
Pin Description BGA217
GPIO_CLK
GPIO_CLK
GPIO_CLK
I/O Type
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Indicates if Schmitt Trigger is enabled.
Note:
• “ST”
Signal
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PB0
PB1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
Primary
Example:
configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”.
That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address
line 20 with Pull-Down.
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is
Signal
Alternate
Dir
SPI0_NPCS0
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
MCI0_CDA
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_CK
PIO Peripheral A
TWCK0
TCLK0
TCLK1
TCLK2
Signal
TIOB1
TIOB2
DRXD
DTXD
TIOA0
TIOA1
TIOA2
TIOB0
TWD0
TXD0
RXD0
RTS0
CTS0
SCK0
TXD1
RXD1
TXD2
RXD2
ERX0
ERX1
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
SPI1_NPCS1
SPI0_NPCS2
SPI0_NPCS1
SPI1_NPCS0
SPI1_NPCS3
SPI1_NPCS2
SPI1_SPCK
SPI1_MISO
SPI1_MOSI
MCI1_CDA
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_DA0
MCI1_CK
PIO Peripheral B
Signal
RTS2
CTS2
RD
TK
TF
TD
RK
RF
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
PIO Peripheral C
ETXEN
Signal
EMDC
ETX0
ETX1
SAM9G35
Dir
O
O
O
O
Signal, Dir, PU,
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
Reset State
PD, ST
11