at91sam9g35-cu ATMEL Corporation, at91sam9g35-cu Datasheet - Page 38

• Manufacturer Part Number: at91sam9g35-cu
• Description: At91sam Arm-based Embedded Mpu
• Manufacturer: ATMEL Corporation

10.13 8-channel DMA (DMAC)
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SAM9G35
• Two DMACs
• DMAC0 is full featured and optimized for memory-to-memory transfers thanks to the 64-word
• DMAC1 is optimized for peripheral-to-memory transfers, without PIP support
• Acting as Two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
• Channel Buffering
• Channel Control
• Transfer Initiation
• Interrupt
FIFO on channel 0
– Source / destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
– Scatter support for placing fields into a system memory area from a contiguous
– Gather support for extracting fields from a system memory area into a contiguous
– User enabled auto-reloading of source, destination and control registers from initially
– Auto-loading of source, destination and control registers from system memory at end
– Unaligned system address to data transfer width supported in hardware
– Picture-In-Picture Mode (on DMAC0 only)
– 16-word FIFO (64-word for channel 0 of DMAC0)
– Automatic packing/unpacking of data to fit FIFO width
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
– Suspend DMA operation
– Programmable DMA lock transfer support
– Support for Software handshaking interface. Memory mapped registers can be used
– Programmable Interrupt generation on DMA Transfer completion Block Transfer
lists
transfer. Writing a stream of data into non-contiguous fields in system memory
transfer
programmed values at the end of a block transfer
of block transfer in block chaining mode
to control the flow of a DMA transfer in place of a hardware handshaking interface
completion, Single/Multiple transaction completion or Error condition
11053AS–ATARM–27-Jul-11