lpc2361 NXP Semiconductors, lpc2361 Datasheet
lpc2361
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lpc2361 Summary of contents
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... In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access (LPC2361 (LPC2362) of SRAM on the ARM local bus for high performance CPU access SRAM for Ethernet interface. Can also be used as general purpose SRAM. ...
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... Product data sheet 2 C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU © NXP B.V. 2008. All rights reserved ...
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... LPC2361FBD100 64 8 LPC2362FBD100 128 32 16 [1] Available as general purpose SRAM for the LPC2361. LPC2361_62_3 Product data sheet Description plastic low profile quad flat package; 100 leads; body 14 plastic low profile quad flat package; 100 leads; body 14 Ethernet USB device + ...
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... AOUT D/A CONVERTER VBAT 2 kB BATTERY RAM power domain 2 power domain 2 RTCX1 RTC RTCX2 OSCILLATOR WATCHDOG TIMER SYSTEM CONTROL (1) LPC2362 only. Fig 1. LPC2361/62 block diagram LPC2361_62_3 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64/128 kB TEST/DEBUG FLASH INTERFACE INTERNAL ...
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... LPC2361FBD100 LPC2362FBD100 25 LPC2361/62 pinning Description Port 0: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. ...
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... SCK — Serial clock for SPI. P0[16] — General purpose digital input/output pin. RXD1 — Receiver input for UART1. SSEL0 — Slave Select for SSP0. SSEL — Slave Select for SPI. Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU 2 S-bus specification . 2 S-bus specification . ...
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... AOUT — D/A converter output. RXD3 — Receiver input for UART3. P0[27] — General purpose digital input/output pin. Output is open-drain. 2 SDA0 — data input/output. Open-drain output (for I Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU 2 S-bus specification . 2 S-bus specification . 2 S-bus specifi ...
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... USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver). USB_PPWR1 — Port Power enable signal for USB port 1. CAP1[1] — Capture input for Timer 1, channel 1. Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU 2 C-bus compliance). © NXP B.V. 2008. All rights reserved. ...
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... P1[29] — General purpose digital input/output pin. 2 USB_SDA1 — USB port 1 I C-bus serial data (OTG transceiver). PCAP1[1] — Capture input for PWM1, channel 1. MAT0[1] — Match output for Timer 0, channel 0. Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU © NXP B.V. 2008. All rights reserved ...
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... P2[6] — General purpose digital input/output pin. PCAP1[0] — Capture input for PWM1, channel 0. RI1 — Ring Indicator input for UART1. TRACEPKT1 — Trace Packet, bit 1. Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU © NXP B.V. 2008. All rights reserved ...
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... Port 4: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU 2 S-bus specification . ...
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... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as trace port after reset. RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2361/62 being in Reset state. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... Pad provides special analog functionality. 7. Functional description 7.1 Architectural overview The LPC2361/62 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently confi ...
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... SRAM block serving as a buffer for the Ethernet controller (available as general purpose SRAM for the LPC2361) and SRAM used by the GPDMA controller or the USB device can be used both for data and code storage. The 2 kB RTC SRAM can be used for data storage only ...
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... RESERVED ADDRESS SPACE 32 kB LOCAL ON-CHIP STATIC RAM (LPC2362 LOCAL ON-CHIP STATIC RAM (LPC2361) 1.0 GB RESERVED FOR ON-CHIP MEMORY TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2362) TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2361) 0.0 GB LPC2361/62 memory map Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU Section 7 ...
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... Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2361/62 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...
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... The value of the output register may be read back as well as the current state of the port pins. LPC2361/62 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • ...
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... DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: LPC2361_62_3 Product data sheet Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU © NXP B.V. 2008. All rights reserved ...
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... Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While the USB is in the Suspend mode, the LPC2361/62 can enter one of the reduced power modes and wake up on USB activity. LPC2361_62_3 Product data sheet Section Rev. 03 — ...
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... Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter. LPC2361_62_3 Product data sheet Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU 2 C interface © NXP B.V. 2008. All rights reserved ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.12 10-bit ADC The LPC2361/62 contain one ADC single 10-bit successive approximation ADC with six channels. 7.12.1 Features • 10-bit successive approximation ADC. • ...
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... UART3 includes an IrDA mode to support infrared communication. 7.15 SPI serial I/O controller The LPC2361/62 each contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. ...
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... The I controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2361/62 supports bit rates up to 400 kbit/s (Fast 2 I C-bus). 7.17.1 Features • ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2361/62. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... Features • LPC2361/62 has one PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow single edge controlled or 3 double edge controlled PWM outputs mix of both types. The match registers also allow: – ...
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... RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2361/62, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock ...
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... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2361/62 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.23.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... Each of the peripherals has its own clock divider which provides even better power control. The LPC2361/62 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the battery RAM ...
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... When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly. 7.23.4.4 Power domains The LPC2361/62 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the battery RAM. ...
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... Code security (Code Read Protection - CRP) This feature of the LPC2361/62 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...
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... AHB2 are the ARM7 and the Ethernet block. 7.24.5 External interrupt inputs The LPC2361/62 include edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. ...
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... The JTAG clock (TCK) must be slower than interface to operate. 7.25.2 Embedded trace Since the LPC2361/62 have significant amounts of on-chip memories not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port. A software debugger allows confi ...
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... V DD(3V3) supply voltage is present [2][3] other I/O pins per supply pin per ground pin based on package heat transfer, not device power consumption human body model; all pins Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4 ...
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... [ [ 0 DD(3V3 DDA [ [9] V < V < DD(3V3) I Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 2.0 3.3 3.6 2.5 3.3 V DDA - - 100 DD(3V3) 2 ...
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... CCLK = 10 MHz CCLK = 72 MHz all peripherals enabled; PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz V = 3.3 V; DD(DCDC)(3V3 amb DC-to-DC converter on DC-to-DC converter off OLS DD(3V3 Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU [1] Min Typ Max - 125 - - ...
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... Conditions 0 V < V < includes V range 1 3 GND L with 33 series resistor; steady state drive drops below 1 grounded. DD(3V3 Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU [1] Min Typ Max - - 5.25 0 0.8 - 2.5 0 0.18 2 ...
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... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 4. Figure Figure 4. Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU Min Typ ...
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... Product data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 (LSB ) IA ideal ). D ). Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU offset error E O (1) 1019 1020 1021 1022 1023 1024 V V DDA SSA 1 LSB = 1024 002aac046 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors AD0[y] Fig 5. Suggested ADC interface - LPC2361/62 AD0[y] pin LPC2361_62_3 Product data sheet LPC23XX 20 k SAMPLE Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU R vsi AD0[y] V EXT 002aac610 © NXP B.V. 2008. All rights reserved ...
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... EOP; see Figure 7 must accept as EOP; see Figure 7 over specified ranges. DD(3V3) Conditions amb measured in SPI Master mode; see Figure 8 Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU Min Typ Max 8.5 - 13.8 7 109 1.3 - 2.0 160 - 175 2 ...
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... Product data sheet t t CHCL CLCX crossover point crossover point differential data to SE0/EOP skew PERIOD FDEOP t su(SPI_MISO) Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU t CHCX t CLCH T cy(clk) 002aaa907 extended source EOP width: t receiver EOP width: t sampling edges 002aad326 FEOPT , t EOPR1 ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC23XX Fig 9. LPC2361/62 USB interface on a self-powered device LPC23XX Fig 10. LPC2361/62 USB interface on a bus-powered device LPC2361_62_3 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D USB_D DD(3V3) ...
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... RSTOUT LPC2361/62 USB_SCL USB_SDA EINTn USB_D+ USB_D Fig 11. LPC2361/62 USB OTG port configuration USB_UP_LED USB_D+ USB_D LPC2361/62 USB_PWRD USB_OVRCR USB_PPWR Fig 12. LPC2361/62 USB host port configuration LPC2361_62_3 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED ISP1301 ...
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... NXP Semiconductors USB_UP_LED USB_CONNECT LPC2361/62 USB_D+ USB_D V BUS Fig 13. LPC2361/62 USB device port configuration LPC2361_62_3 Product data sheet Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU USB-B D connector V BUS 002aad968 © NXP B.V. 2008. All rights reserved. ...
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... scale (1) ( 0.27 0.20 14.1 14.1 16.25 16.25 0.5 0.17 0.09 13.9 13.9 15.75 15.75 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU detail 0.75 1.15 1 0.2 0.08 0.08 0.45 0.85 EUROPEAN PROJECTION SOT407 (1) (1) ...
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... Pulse Width Modulator Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU © NXP B.V. 2008. All rights reserved ...
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... Table updated Table note 8. OHS OLS • Figure 6: removed figure note row “V 20080804 Product data sheet Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU Change notice Supersedes - LPC2361_62_2 - LPC2361_62_1 = 1.8 V” © NXP B.V. 2008. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. SoftConnect — trademark of NXP B.V. GoodLink — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU © NXP B.V. 2008. All rights reserved ...
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... Application information . . . . . . . . . . . . . . . . . 42 11.1 Suggested USB interface solutions . . . . . . . . 42 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 45 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 47 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 48 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 48 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 15.3 Disclaimers 15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Rev. 03 — 11 November 2008 LPC2361/62 Single-chip 16-bit/32-bit MCU continued >> © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 11 November 2008 Document identifier: LPC2361_62_3 ...