lpc2888fet180 NXP Semiconductors, lpc2888fet180 Datasheet
lpc2888fet180
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lpc2888fet180 Summary of contents
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LPC2880; LPC2888 16/32-bit ARM microcontrollers cache flash, Hi-Speed USB 2.0 device, and SDRAM memory interface Rev. 02 — 21 November 2006 1. General description The LPC2880/2888 is an ARM7-based microcontroller for portable applications requiring ...
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... Watchdog timer with interrupt and/or reset capabilities. 3. Ordering information Table 1. Type number LPC2880FET180 LPC2888FET180 3.1 Ordering options Table 2. Type number LPC2880FET180 LPC2888FET180 LPC2880_LPC2888_2 Preliminary data sheet 16/32-bit ARM microcontrollers with external memory interface Ordering information Package Name Description TFBGA180 plastic thin fine-pitch ball grid array package; 180 balls ...
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... NXP Semiconductors 4. Block diagram LPC2880/2888 (1) FLASH SRAM FLASH SRAM INTERFACE INTERFACE +1 DC-TO-DC 3.3 V, CONVERTER 1.8 V START, STOP WATCHDOG TIMER SYSTEM CONTROL EVENT ROUTER CLOCK XTALI OSCILLATOR GENERATION AND PLLs XTALO UNIT X32I REAL-TIME OSCILLATOR CLOCK X32O GENERAL Px.y PURPOSE I/O 10-BIT A/D AIN[4:0] ...
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... Row D 1 LD4/P4[8] LPC2880_LPC2888_2 Preliminary data sheet 16/32-bit ARM microcontrollers with external memory interface ball A1 index area LPC2880FET180 J K LPC2888FET180 Transparent top view Pin allocation table Pin Symbol 2 D1/P0[ SS2(EMC) 10 MCLKO/P1[14] 14 A15/P0[31] 18 A6/P0[22] ...
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... NXP Semiconductors Table 3. Pin Symbol A4/P0[20] Row A1/P0[17] Row DATO/P3[6] Row WSI/P3[2] Row BCKI/P3[1] Row J 1 MD2/P5[ SDA Row K 1 RTS/P6[ P2[1] Row START Row M 1 VREFN(DAC DCDC_V Row N 1 i.c. ...
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... NXP Semiconductors Table 3. Pin Symbol 17 DCDC_LX1 Row Row T 1 AINR 5 JTAG_TDI JTAG_TRST 17 DM Row U 1 VREF(DADC) 5 AIN4 JTAG_TDO 17 DP Row V 1 VREFN(DADC XTALO [1] These pins are connected internally and must be left unconnected in an application. ...
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... NXP Semiconductors Table 4. Pin description …continued Signal name Ball # Type Analog in (single converter) AIN0 U7 I AIN1 T7 I AIN2 U6 I AIN3 T6 I AIN4 V10 P DD(ADC3V3) V U10 P SS(ADC) Analog out (dual channel) AOUTL M2 O AOUTR M3 O VREFN(DAC VREFP(DAC DD(DAC3V3) ...
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... NXP Semiconductors Table 4. Pin description …continued Signal name Ball # Type D0/P0[ D1/P0[1] A2 D2/P0[2] B2 D3/P0[3] A3 D4/P0[4] A4 D5/P0[5] B4 D6/P0[6] A5 D7/P0[7] B5 D8/P0[ D9/P0[9] C5 D10/P0[10] C6 D11/P0[11] B6 D12/P0[12] C7 D13/P0[13] B7 D14/P0[14] C8 D15/P0[15] B8 A0/P0[16] E16 FO A1/P0[17] E17 A2/P0[18] E18 A3/P0[19] D16 A4/P0[20] D17 A5/P0[21] D18 A6/P0[22] A18 A7/P0[23] B18 A8/P0[24] C18 A9/P0[25] B17 A10/P0[26] C17 A11/P0[27] B16 A12/P0[28] C16 A13/P0[29] B15 A14/P0[30] ...
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... NXP Semiconductors Table 4. Pin description …continued Signal name Ball # Type DQM0/P1[10] C12 FO DQM1/P1[11] A11 FO DYCS/P1[ MCLKO/P1[14] A10 FO OE/P1[18] A17 FO RAS/P1[17 RPO/P1[19 STCS0/P1[ STCS1/P1[ STCS2/P1[7] B11 FO WE/P1[15] C11 FO GPIO and mode control MODE1/P2[2] K18 FI MODE2/P2[3] J16 FI P2[0] K16 FI P2[1] K17 ...
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... NXP Semiconductors Table 4. Pin description …continued Signal name Ball # Type MCMD/P5[ MD0/P5[ MD1/P5[ MD2/P5[ MD3/P5[ MCLK/P5[ Oscillator (32.768 kHz) X32I V7 I X32O DD(OSC321V8 SS(OSC32) Oscillator (main) XTALI T10 I XTALO DD(OSC1V8) ...
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... NXP Semiconductors Table 4. Pin description …continued Signal name Ball # Type Digital power and ground DD1(CORE1V8) V V15 P DD1(FLASH1V8) V A16 P DD1(EMC DD1(IO3V3) V V11 P DD2(CORE1V8 DD2(EMC) V V16 P DD2(FLASH1V8 DD2(IO3V3) V V14 P DD3(IO3V3) V J18 P DD4(IO3V3 DD5(IO3V3 DD6(IO3V3 SS1(CORE) V A15 ...
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... NXP Semiconductors Lower speed peripheral functions are connected to the APBs. The four AHB-to-APB bridges interface the APBs to the AHB. 6.1.1 ARM7TDMI processor The ARM7TDMI is a general purpose 32-bit microprocessor that offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISCs ...
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... NXP Semiconductors The boot code in this ROM reads the state of the mode inputs and accordingly does one of the following: 1. Starts execution in internal flash 2. Starts execution in external memory 3. Performs a hardware self-test Downloads code from the USB interface into on-chip RAM and transfers control to the downloaded code ...
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... NXP Semiconductors 4.0 GB reserved peripherals includes AHB and 4 APB buses 2.0 GB reserved dynamic memory bank reserved static memory bank external memory (second instance) reserved static memory bank reserved static memory bank 1.0 GB reserved dynamic memory bank reserved static memory bank ...
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... NXP Semiconductors 6.3 Cache The CPU of the LPC2880/2888 has been extended with a 2-way set-associative cache. The cache size and can store both data and instruction code. If code that is being executed is present in the cache from a previous execution, the CPU will not experience code fetch waits. Similarly, if requested data is present in the cache, the CPU will not experience a data access wait ...
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... NXP Semiconductors Programming the flash in a running application is accomplished via a register interface on the APB bus. The flash module can generate an interrupt request when burning or erasing is completed. The flash memory contains a buffer to allow for faster execution. Information is read from the flash 128 bits at a time. The buffer holds this entire amount, which can represent four 32-bit ARM instructions. These captured instructions can them be executed without fl ...
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... NXP Semiconductors 6.6 GPIO Many device pins that are not needed for a specific peripheral function can be used as GPIOs. These pins can be controlled by the MODE registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The current state of the port pins may be read back via the PIN registers ...
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... NXP Semiconductors All 99 Pending signals are presented to each of the five output logic blocks. Each output logic block includes a set of four Interrupt Output Mask Registers, each set totalling 99 bits, that control whether each signal applies to that output. These are logically ANDed with the corresponding Pending signals, and the 99 results in each logic block are logically ORed to make the output of the block ...
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... NXP Semiconductors 6.10.1 Features • Optionally resets chip (via Clock Generation Unit) if not periodically reloaded. • Optional interrupt via Event Router. • 32-bit Prescaler and 32-bit Counter allow extended watchdog period. 6.11 Real-time clock The Real-time clock is a set of counters for measuring time when system power is on, and optionally when it is off ...
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... NXP Semiconductors • GPDMA channels can be programmed to swap data between big- and little-endian formats during a transfer. • An interrupt to the processor can be generated on DMA completion, when a DMA channel is halfway to completion, or when a DMA error has occurred. 6.13 UART and IrDA The LPC2880/2888 contains one UART with baud rate generator and IrDA support. ...
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... NXP Semiconductors • Input multiplexing among 5 pins. • Power-down mode. • Measurement range 3.3 V. • 10-bit conversion time • Single or continuous conversion mode. 6.16 Analog I/O The analog I/O system includes an I dual ADC, and a dual DAC. Each channel includes a separate 4 sample FIFO. ...
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... NXP Semiconductors 6.17.1 Features • Fully compliant with USB 2.0 specification (high-speed and full-speed). • 8 logical endpoints = 16 physical endpoints. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Endpoint type selection by software • Endpoint maximum packet size setting by software • Supports Soft Connect feature (requires an external 1.5 k resistor between the CONNECT pad and 3.3 V). • ...
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... NXP Semiconductors 6.20 Clocking and power control Clocking in the LPC2880/2888 is controlled by a versatile CGU, so that system and peripheral requirements may be met while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed, and may be enabled and disabled by selected events through the Event Router. ...
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... NXP Semiconductors The low power PLL takes the input clock and multiplies higher frequency ( 32), then divides it down ( provide the output clock used by the CGU. The output frequency of this PLL can range from 10 MHz to 320 MHz. Functional blocks may have limitations below this upper limit ...
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... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V external memory controller DD(EMC) supply voltage V analog input voltage IA V input voltage I input voltage I supply current DD I ground current ...
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... NXP Semiconductors 8. Static characteristics Table 6. Static characteristics +85 C, unless otherwise specified. a Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V external memory controller supply DD(EMC) voltage I LOW-state input current IL I HIGH-state input current IH I OFF-state output current ...
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... NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. a Symbol Parameter I DAC output supply current DDO(DAC) I analog output supply current DDOA [1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. [2] Applies to pins V ...
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... NXP Semiconductors 9. Dynamic characteristics Table 7. Dynamic characteristics +85 C, unless otherwise specified. a Symbol Parameter External clock f external clock frequency ext Port pins t rise time r t fall time f [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors 10. Package outline TFBGA180: plastic thin fine-pitch ball grid array package; 180 balls; body 0.8 mm ball A1 index area ball index area 2 4 DIMENSIONS (mm are the original dimensions) A UNIT ...
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... NXP Semiconductors 11. Abbreviations Table 8. Acronym ADC AMBA AHB APB CISC CGU DAC DMA FIQ GPIO IrDA IRQ JTAG LCD PLL RISC SD/MMC SDRAM SOF SRAM UART USB LPC2880_LPC2888_2 Preliminary data sheet 16/32-bit ARM microcontrollers with external memory interface Acronym list Description ...
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... Release date LPC2880_LPC2888_2 20061121 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Figure 1 “Block • Table 3 “Pin allocation • ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . 11 6.1 Architectural overview 6.1.1 ARM7TDMI processor . . . . . . . . . . . . . . . . . . 12 6.1.2 On-chip flash memory system . . . . . . . . . . . . 12 6.1.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 Memory map 6.3 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 ...