c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 104

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

C8051T610/1/2/3/4/5/6/7
SFR Definition 10.2. RSTSRC: Reset Source
104
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read),
read-modify-write instructions read and modify the source enable only.
Bit7
R
-
UNUSED. Read = 0b. Write = don’t care.
MEMERR: EPROM Error Indicator.
0: Source of last reset was not an EPROM error.
1: Source of last reset was an EPROM error.
C0RSEF: Comparator0 Reset Enable and Flag.
Write
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active-low).
Read
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
SWRSF: Software Reset Force and Flag.
Write
0: No Effect.
1: Forces a system reset.
Read
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last was a write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
Write:
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected.
Read:
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. This may be due to a true power-on reset or a
V
reset. Writing this bit enables/disables the V
Write:
0: Disable VDD monitor as a reset source (does not disable VDD monitor circuit).
1: Enable VDD monitor as a reset source (does not enable VDD monitor circuit).
Read:
0: Last reset was not a power-on or V
1: Last reset was a power-on or V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
DD
MEMERR C0RSEF
monitor reset. In either case, data memory should be considered indeterminate following the
Bit6
R
R/W
Bit5
SWRSF
R/W
Bit4
DD
monitor reset; all other reset flags indeterminate.
DD
WDTRSF MCDRSF
Rev. 0.3
monitor reset.
Bit3
R
DD
monitor.
R/W
Bit2
PORSF
R/W
Bit1
PINRSF
Bit0
R
SFR Address:
Reset Value
Variable
0xEF