mc9s08dz32 Freescale Semiconductor, Inc, mc9s08dz32 Datasheet - Page 206

• Manufacturer Part Number: mc9s08dz32
• Description: Hcs08 Microcontrollers 8-bit Can Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.3.3
206
Reset
IICEN
TXAK
RSTA
Field
IICIE
MST
TX
7
6
5
4
3
2
W
R
IICEN
IIC Control Register (IICC1)
IIC Enable. The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled
1 IIC is enabled
IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled
1 IIC interrupt request enabled
Master Mode Select. The MST bit changes from a 0 to a 1 when a start signal is generated on the bus and master
mode is selected. When this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation
changes from master to slave.
0 Slave mode
1 Master mode
Transmit Mode Select. The TX bit selects the direction of master and slave transfers. In master mode, this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high.
When addressed as a slave, this bit should be set by software according to the SRW bit in the status register.
0 Receive
1 Transmit
Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA during data acknowledge cycles
for master and slave receivers.
0 An acknowledge signal is sent out to the bus after receiving one data byte
1 No acknowledge signal response is sent
Repeat start. Writing a 1 to this bit generates a repeated start condition provided it is the current master. This bit
is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration.
0
7
= Unimplemented or Reserved
IICIE
0
6
Figure 11-5. IIC Control Register (IICC1)
Table 11-5. IICC1 Field Descriptions
MC9S08DZ60 Series Data Sheet, Rev. 3
MST
0
5
TX
0
4
Description
TXAK
3
0
RSTA
0
0
2
Freescale Semiconductor
0
0
1
0
0
0