mc9s08dz32 Freescale Semiconductor, Inc, mc9s08dz32 Datasheet - Page 86

• Manufacturer Part Number: mc9s08dz32
• Description: Hcs08 Microcontrollers 8-bit Can Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 6 Parallel Input/Output Control
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.2
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pull-ups, slew rate, and drive
strength for the pins.
An internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up
enable register (PTxPEn). The pull-up device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up
enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function.
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the MCU are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
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Pull-up, Slew Rate, and Drive Strength
Slew rate reset default values may differ between engineering samples and
final production parts. Always initialize slew rate control to the desired
value to ensure correct operation.
Port Read
BUSCLK
Data
Figure 6-1. Parallel I/O Block Diagram
MC9S08DZ60 Series Data Sheet, Rev. 3
PTxDDn
D
D
PTxDn
Q
Q
NOTE
1
0
Synchronizer
Output Enable
Output Data
Freescale Semiconductor
Input Data