mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet
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mc9s12uf32 Summary of contents
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... Commercial: Typically 5 year applications - personal computers, PDA’s, portable telecom products, consumer electronics, etc. Industrial: Typically 10 year applications - installed telecom equipment, work stations, servers, etc. These products can also be used for Commercial applications. Automotive: Qualified per automotive industry standard methods. MC9S12UF32 V01.05 Original Release Date: 17 JAN 2002 Revised: 03 Dec 2004 TSPG - 8/16 Bit MCU Design, HKG Freescale Semiconductor, Inc ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale Semiconductor, Inc. Freescale Semiconductor, Inc Equal Opportunity/Affirmative Action Employer. Freescale Semiconductor Author Initial Version Modifi ...
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Release Date Number 01.00 21AUG03 Y.H. Cheng 01.01 28NOV03 Wai-On Law 01.02 23MAR04 Y.H. Cheng 01.03 20APR04 Wai-On Law 01.04 10MAY04 Wai-On Law 01.05 03DEC04 Wai-On Law Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Author - Removed ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 4 Freescale Semiconductor ...
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Table of Contents Section 1 Introduction 1.1 Overview ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.4.20 PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output . . . . . . . . . . . . . . . . . . . . ...
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PU0 / CFWAIT / ATAIORDY — Port U I/O Pin .66 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.5.34 PS7 / CFRDY(CFIREQ) / ATAINTQ / MSSDIO — Port S I/O Pin .73 2.5.35 PS6 / CFWE / ...
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Reset Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Section 20 USB2.0 Controller (USB20D6E2F) Block Description 20.1 Device-specific information .93 Section 21 Voltage Regulator (VREG_U) Block Description 21.1 Device-specific information .94 Section 22 Schematic and PCB Layout Design Recommendations 22.1 Schematic Design with the MC9S12UF32 and a USB interface . . . . . . . . . . . . . . . . . .94 22.1.1 Power Supply Notes .95 22.1.2 Clocking Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 22.2 PCB Design Recommendation .96 Appendix A Electrical Characteristics A ...
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A.2.1 NVM timing ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 12 Freescale Semiconductor ...
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... List of Figures Figure 0-1 Order Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 1-1 MC9S12UF32 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 1-2 MC9S12UF32 Memory Map (Application Example .25 Figure 2-1 Pin Assignments in 100-pin LQFP .49 Figure 2-2 Pin Assignments in 64-pin LQFP .50 Figure 2-3 Supply rails for various I/O pins of 100-pin package . . . . . . . . . . . . . . . . . . . . . .76 Figure 2-4 Supply rails for various I/O pins of 64-pin package . . . . . . . . . . . . . . . . . . . . . . .76 Figure 3-1 Clock Connections ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 14 Freescale Semiconductor ...
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... Configuration selection in 100-pin option .47 Table 2-2 Configuration selection in 64-pin option .48 Table 2-3 100-pin Signal Properties .51 Table 2-4 64-pin Signal Properties .54 Table 2-5 MC9S12UF32 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . .74 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 5-2 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 11-1 Queue Channel n Request Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Table 22-1 Recommended decoupling capacitor choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table A-1 Absolute Maximum Ratings ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 16 Freescale Semiconductor ...
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... Preface The SoC Guide provides information about the MC9S12UF32 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block Guides of the implemented modules effort to reduce redundancy all module specific information is located only in the respective Block Guide ...
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... MC9S12 UF32 FU Figure 0-1 Order Part Number Coding Table 0-2 lists the part number coding based on the package. Part Number MC9S12UF32PB MC9S12UF32PU 18 Package Option Device Title Controller Family Table 0-2 Part Number Coding Package Description 64LQFP MC9S12UF32 100LQFP MC9S12UF32 Package Options PB = 64LQFP PU = 100LQFP Freescale Semiconductor ...
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... Section 1 Introduction 1.1 Overview The MC9S12UF32 microcontroller unit (MCU) is USB2.0 device for memory card reader and ATA/ATAPI interface applications. This device is composed of standard on-chip modules including a 16-bit central processing unit (HCS12 CPU), 32k bytes of Flash EEPROM, 3.5k bytes of RAM, USB2.0 interface, Integrated Queue Controller (IQUE) block with 1.5k bytes RAM buffer for USB Bulk data ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 - Used as a contiguous 3.5k byte SRAM with misaligned access support - Configurable to 1084 byte SRAM and 2000 x 10 bit SRAM for Smartmedia logical to physical address translation and ...
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Endpoint 0 IN, endpoint 0 OUT, endpoint 2 and endpoint 3 each has an independent 64 bytes fixed endpoint buffer. • ATA5 Host Controller Interface (ATA5HC) – Support PIO mode – Support Multi-word DMA mode 0 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 • 64-Pin LQFP package – User selectable subset of modules available. – I/O pins with 5V only drive capability and 1 input only 5V pin. – ...
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... Some pins are not available in 100-pin package. * IPbus runs at 1/2 frequency of S12 core bus, which is controlled by REFDV register of CRG_U module. *Qbus refers to the data transfer channels between IQUE and USB/ATA5HC/CFHC/MSHC/SDHC/SMHC. Figure 1-1 MC9S12UF32 Block Diagram Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 I/O Driver 3 ...
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... System on a Chip Guide — 9S12UF32DGV1/D V01.05 1.5 Device Memory Map Table 1-1 shows the device memory map of the MC9S12UF32 after reset. Address $0000 - $000F HCS12 Multiplexed External Bus Interface $0010 - $0014 HCS12 Module Mapping Control $0015 - $0016 HCS12 Interrupt $0017 - $0018 Reserved ...
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... The figure shows an example of an application memory map with the following register setting. This is not the map out of reset. INITRG = $00 INITRM = $20 INITEE = $11 PPAGE = $3E Figure 1-2 MC9S12UF32 Memory Map (Application Example) Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table 1-1 Device Memory Map EXT VECTORS ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 1.5.1 Detailed Register Map $0000 - $000F Address Name Read: $0000 PORTA Write: Read: $0001 PORTB Write: Read: $0002 DDRA Write: Read: $0003 DDRB Write: Read: $0004 - Reserved $0007 Write: Read: ...
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Address Name Read: $0015 ITCR Write: Read: $0016 ITEST Write: $0017 - $0017 Address Name Read: $0017 Reserved Write: $0018 - $0018 Address Name Read: $0018 Reserved Write: $0019 - $0019 Address Name Read: Reserved for $0019 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $001F - $001F Address Name Read: $001F HPRIO Write: $0020 - $0027 Address Name Read: $0020 - Reserved $0027 Write: $0028 - $002F Address Name Read: $0028 BKPCT0 Write: Read: $0029 BKPCT1 ...
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Address Name Read: $0034 Reserved Write: Read: $0035 REFDV Write: Read: TOUT7 CTFLG $0036 Test Only Write: Read: $0037 CRGFLG Write: Read: $0038 CRGINT Write: Read: $0039 CLKSEL Write: Read: $003A Reserved Write: Read: $003B RTICTL Write: ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $0040 - $006F Address Name Read: $004A TCTL3 Write: Read: $004B TCTL4 Write: Read: $004C TIE Write: Read: $004D TSCR2 Write: Read: $004E TFLG1 Write: Read: $004F TFLG2 Write: Read: $0050 TC0 ...
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Address Name Read: $0063 PACNT (lo) Write: Read: $0064 Reserved Write: Read: $0065 Reserved Write: Read: $0066 Reserved Write: Read: $0067 Reserved Write: Read: $0068 Reserved Write: Read: $0069 Reserved Write: Read: $006A Reserved Write: Read: $006B ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $00C8 - $00CF Address Name Read: $00CD SCISR2 Write: Read: $00CE SCIDRH Write: Read: $00CF SCIDRL Write: $00D0 - $00FF Address Name Read: $00D0 - Reserved $00FF Write: $0100 - $010F Address ...
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Address Name Read: $0110 - Reserved $011B Write: $011C - $011F Address Name Read: $011C SMRAMCFG Write: Read: $011D SMRAMSTAT Write: Read: $011E - Reserved $011F Write: $0120 - $01BF Address Name Read: $0120 - Reserved $01BF ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $01C0 - $01FF Address Name Read: $01CC HDMA1 (hi) Write: Read: $01CD HDMA1 (lo) Write: Read: $01CE HDMA2 (hi) Write: Read: $01CF HDMA2 (lo) Write: Read: HDMA3 $01D0 (hi) Write: Read: $01D1 ...
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Address Name Read: $01E5 HUDMA9 (lo) Write: $01E6 - Read: Reserved $01ED Write: 1 Read: DCTR/DASR $01EE Write: (hi) 1 Read: DCTR/DASR $01EF Write: (lo) Read: 1 $01F0 DDR (hi) Write: Read: 1 $01F1 DDR (lo) Write: ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $0200 - $023F Address Name Read: $0200 IQUECR Write: Read: $0201 Reserved Write: Read: $0202 QC1DR (hi) Write: Read: $0203 QC1DR (lo) Write: Read: $0204 QC1BP (hi) Write: Read: $0205 QC1BP (lo) ...
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Address Name Read: $0219 QC3BP (lo) Write: Read: $021A QC3EP (hi) Write: Read: $021B QC3EP (lo) Write: Read: $021C QC3CR Write: Read: $021D QC3SR Write: Read: $021E QC3SZB Write: Read: $021F QC3REQ Write: Read: $0220 QC4DR (hi) ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $0200 - $023F Address Name Read: $0230 QC12DSHR Write: Read: $0231 QC34DSHR Write: Read: $0232 - Reserved $023F Write: $0240 - $027F Address Name Read: $0240 PTT Write: Read: $0241 PTIT Write: ...
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Address Name Read: $0255 PPSJ Write: Read: $0256 Reserved Write: Read: $0257 MODRR Write: Read: $0258 PTP Write: Read: $0259 PTIP Write: Read: $025A DDRP Write: Read: $025B RDRP Write: Read: $025C PERP Write: Read: $025D PPSP ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $0240 - $027F Address Name Read: $0271 PTIS Write: Read: $0272 DDRS Write: Read: $0273 RDRS Write: Read: $0274 PERS Write: Read: $0275 PPSS Write: Read: $0276 - Reserved $0277 Write: Read: ...
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Address Name Read: $0289 CFCR (lo) Write: Read: $028A CFBBAR (hi) Write: Read: $028B CFBBAR (lo) Write: Read: $028C CFBSR (hi) Write: Read: $028D CFBSR (lo) Write: Read: $028E CFPMR (hi) Write: Read: $028F CFPMR (lo) Write: ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $02A0 - $02AF Address Name Read: $02AA MSC1 Write: Read: $02AB MSS1 Write: Read: $02AC MSACMD (hi) Write: Read: $02AD MSACMD (lo) Write: Read: $02AE Reserved Write: Read: $02AF Reserved Write: $02B0 ...
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Address Name Read: SDCLKCON $02C4 (hi) Write: SDCLKCON Read: $02C5 (lo) Write: Read: SDCMDATCO $02C6 N (hi) Write: Read: SDCMDATCO $02C7 N (lo) Write: Read: $02C8 SDRTOUT (hi) Write: Read: $02C9 SDRTOUT (lo) Write: SDRDTOUT Read: $02CA ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $02E0 - $02FF Address Name $02E0 - Read: Reserved $02FF Write: $0300 - $03FF Address Name Read: $0300 UMCR (hi) Write: Read: $0301 UMCR (lo) Write: Read: $0302 UMSR1 (hi) Write: Read: ...
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Address Name Read: UNCIR (bit $0311 23-16) Write: UNCIR (bit Read: $0312 15-8) Write: Read: $0313 UNCIR (bit 7-0) Write: Read: UNASR (bit $0310 31-24) Write: Read: UNASR (bit $0311 23-16) Write: Read: UNASR (bit $0312 15-8) ...
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... The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID number. Device MC9S12UF32 MC9S12UF32 MC9S12UF32 MC9S12UF32 NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers ...
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Section 2 Signal Description The 9S12UF32 has two package options, the first one is a full featured 100-pin package and the second one in a low cost 64-pin package. In the 100-pin option, three primary software selectable configurations are available ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 • USB 2 bridge Below table shows a summary of how the above configurations can be selected. Table 2-2 Configuration selection in 64-pin option Configuration ATA bridge MODRR Recommended IO ...
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... SCD/ACFD09/AATAD09/PP1 23 SCE/ACFD10/AATAD10/PP2 24 SWP/ACFD11/AATA11/PP3 25 SCLE/ACFD12/AATA12/PP4 Note: Not all pin functions are shown in the diagram. Please refer to sections 2-2 and 2-4 for details. Figure 2-1 Pin Assignments in 100-pin LQFP Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 MC9S12UF32 100LQFP PS7/CFRDY/ATAINTQ 75 PS6/CFWE/ATADMARQ 74 PS5/CFIORW/ATAIORW 73 PS4/CFIORD/ATAIORD 72 PS3/CFCE2/ATACS1 71 PS2/CFIOIS16 ...
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... SDAT2/CFA2/ATADA2/PQ2 SDAT3/CFIORD/ATAIORD/PQ3 SDAT4/CFA4/ATADMACK/IOC4PQ4 SDAT5/CFA5//SDCMD/PQ5 SDAT6/CFA6/SDCLK/PQ6 SDAT7/CFA7/IOC7/PQ7 Note: Not all pin functions are shown in the diagram. Please refer to sections 2-3 and 2-5 for details. Figure 2-2 Pin Assignments in 64-pin LQFP MC9S12UF32 9 64 LQFP PS7/CFRDY/ATAINTQ/MSSDIO 47 PS6/CFWE/ATADMARQ/CSCLK 46 PS5/TXD 45 ...
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Signal Properties Summary for 100-pin Package Pin Name Pin Name Pin Name Function Function Function EXTAL — — XTAL — — 1 — — TEST VREGEN — — PE7 NOACC — PE6 IPIPE1 MODB PE5 IPIPE0 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 Pin Name Pin Name Pin Name Function Function Function PJ0 MSBS CFIORW PJ1 MSSDIO CFCE1 3 MSSCLK PJ2 CFCE2 PM5 SDDATA3 CFIORD PM4 SDDATA2 CFIOIS16 PM3 SDDATA1 CFINPACK PM2 ...
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Pin Name Pin Name Pin Name Function Function Function PR[2] CFA[5] RXD PR[3] CFA[6] TXD PR[7:4] CFA[10:7] IOC[7:4] CFRDY/ PS7 ATAINTQ IREQ PS6 CFWE ATADMARQ PS5 CFIOWR ATAIOWR PS4 CFIORD ATAIORD PS3 CFCE2 ATACS1 PS2 CFIOIS16 — ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.3 Signal Properties Summary for 64-pin Package Pin Name Pin Name Pin Name Function Function Function EXTAL — — XTAL — — 1 — — TEST PE7 NOACC — ...
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Pin Name Pin Name Pin Name Function Function Function ADDR8/ PA0 CFD8 DATA8 ADDR[7:0]/ PB[7:0] CFD[7:0] DATA[7:0] RESET — — BKGD MODC TAGHI RPU — — RREF — — DPF — — DPH — — DMF — ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 Pin Name Pin Name Pin Name Function Function Function PQ4 SDAT4 CFA4 PQ3 SDAT3 CFIORD PQ2 SDAT2 CFA2 PQ1 SDAT1 CFA1 PQ0 SDAT0 CFA0 CFRDY/ PS7 MSSDIO IREQ PS6 ...
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Detailed Signal Descriptions for 100-pin package 2.4.1 EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.4.8 DPF - USB Full Speed D+ data line DPF is the D+ analog input output line for full speed data communication in the USB physical layer module. This line is also ...
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I/O Pins PA[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. In single chip mode, this port can be configured as data bus ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.4.21 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 / Low-Byte Strobe (LSTRB) PE3 can be used as a general-purpose I/O in all modes and is an input with ...
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PJ1 / MSSDIO - Port J I/O Pin 1 PJ1 is a general purpose input or output pin. When the MSHC module is enabled it becomes the serial data line (MSSDIO) for the MSHC module. While in reset and ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.4.32 PP6 / SWE / ACFD14 / AATAD14— Port P I/O Pin 6 PP6 are general purpose input or output pin. When enabled in the SMHC module, the PP6 pin becomes the ...
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PP1 / SCD / ACFD9 / AATAD9— Port P I/O Pin 1 PP1 are general purpose input or output pin. When enabled in the SMHC module, the PP1 pin becomes the card detect pin, SCD. When the SMHC is ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.4.42 PR[3] / CFA[6] / TXD — Port R I/O Pins [3] PR[3] is general purpose input or output pin. When enabled in the CFHC module, the PR[3] pin becomes the Compact ...
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Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the ATA5HC Block Guide for information about pin configurations. 2.4.47 PS4 / CFIORD / ATAIORD — Port S I/O Pin 4 PS4 is a general purpose ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.4.52 PT[3:0] / IOC[3:0]— Port T I/O Pins [3:0] PT[3:0] are general purpose input or output pins. When the Timer system (TIM) is enabled they can also be configured as the TIM ...
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Detailed Signal Descriptions for 64-pin package 2.5.1 EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.5.8 DPH - USB High Speed D+ data line DPH is the D+ analog input output line for high speed data communication in the USB physical layer module. This line will be ...
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PA[7] / ADDR[15] / DATA[15] / CFD[15] / ATAD[15] — Port A I/O Pins PA[ general purpose input or output pin. In MCU expanded modes of operation, this pin is used for the multiplexed external address and ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 used as a timing reference. The ECLK frequency is equal to 1/2 the crystal frequency out of reset. The ECLK output function depends upon the settings of the NECLK bit in the ...
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Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the SMHC Block Guide for information about pin configurations. 2.5.24 PJ1 / ATACS0 / SCLE / CFCE1 - Port J I/O Pin 1 PJ1 is ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 2.5.29 PQ6 / SDAT6 / CFA6 / SDCLK / IOC6 — Port Q I/O Pins 6 PQ4 is a general purpose input or output pin. This pin can be used as IOC6 ...
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PS7 / CFRDY(CFIREQ) / ATAINTQ / MSSDIO — Port S I/O Pin 7 PS7 is a general purpose input or output pin. This pin can be configured as MSSDIO signal of the MSHC module; ATAINTQ signal of the ATA5HC ...
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... Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the ATA5HC Block Guide for information about pin configurations. 2.6 Power Supply Pins MC9S12UF32 power and ground pins are described below. Table 2-5 MC9S12UF32 Power and Ground Connection Summary Nominal Mnemonic Voltage VDDR 5 ...
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VDD - Core Power Pin This 2.5v supply is derived from the internal voltage regulator. There is no static load on this pin allowed. The internal voltage regulator is turned off if VREGEN is tied to ground. In that ...
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... PQ1 PQ2 PQ3 PQ4 PQ5 PQ6 PQ7 Figure 2-4 Supply rails for various I/O pins of 64-pin package VDDA VDDR MC9S12UF32 100LQFP VDD3X 1 2 VDDR VDDA MC9S12UF32 9 64 LQFP VDD3X 15 VDDX 16 PS7 75 PS6 74 PS5 73 PS4 72 PS3 71 PS2 70 PS1 69 ...
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Section 3 System Clock Description The clock is generated by the USB20PHY analog sub-block in the USB20D6E2F module.The Clock and Reset Generator distributes the internal clock signals for the core and all peripheral modules. Figure 3-1shows the clock connections from ...
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... Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12UF32. Each mode has an associated default memory map and external bus configuration. In addition each operating mode, with the exception of Special Peripheral Mode (SPM), can be configured for low power operation by entering one of two low power sub-modes ...
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Normal Operating Modes These modes provide three operating configurations: Normal Single-Chip Mode, Normal Expanded Wide Mode, and Normal Expanded Narrow Mode. Background debug (BDM) is available in all three normal modes, but must first be enabled for some operations ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 The Port E bit 3 pin can be re-configured as the LSTRB bus control signal by writing “1” to the LSTRE bit in the PEAR register. The default condition of this pin ...
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I/O. Writes to the bus control enable bits in the PEAR register in special mode are restricted. 4.2.1.5 Emulation Expanded Narrow Mode Expanded narrow modes are intended to allow connection of single 8-bit external memory ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 The pins associated with Port E bits and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes ...
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Protection of the contents of FLASH, • Operation in single-chip mode, • Operation from external memory with internal FLASH disabled. The user must be reminded that part of the security must lie with the user’s code. An extreme example ...
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... Low Power Modes There are two low power modes available on the MC9S12UF32: Stop and Wait Please see Table A-8 for device operating characteristics in Stop and Wait modes. Consult the CRG_U Block Guide and the respective Block Guide for information on the module behavior in Stop and Wait Mode ...
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Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts. Both local masking and CCR masking are included as listed in Table 5-1. System resets can ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 $FFCC, $FFCD USB Endpoint 0 OUT $FFCA, $FFCB USB Endpoint 2 $FFC8, $FFC9 USB Endpoint 3 $FFC6, $FFC7 $FFC4, $FFC5 USB Endpoint 4 $FFC2, $FFC3 USB Endpoint 5 $FFC0, $FFC1 USB Endpoint ...
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Resets Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a system reset are summarized in Table 5-2. 5.3.1 Reset Summary Table Reset Power-on Reset External Reset COP Watchdog Reset 5.3.2 Effects ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 Section 6 HCS12 Core Block Description 6.1 CPU12 Block Description Consult the CPU12 Reference Manual for information about the Central Processing Unit.When the CPU12 Reference Manual refers to cycles, this is equivalent ...
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... The register spaces for the CFHC is located at addresses $0280-$029F. The module inputs CD1, CD2, CVCC, SPKR, STSCHG, VS1, VS2 and the module output CRESET are not used in MC9S12UF32 (i.e. not connected to chip I/O pins) and are internally tied to constant values. User can use GPIO pins for these CF card interface if necessary. ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 10.1 Device-specific information The FTS32K is part of the HCS12 Bus domain. The register spaces for the FTS32K is located at addresses $0100-$010F. The memory spaces for the FTS32K is located at ...
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Section 12 Memorystick Host Controller (MSHC) Block Description Consult the MSHC Block Guide for information about the Memorystick host controller module. 12.1 Device-specific information The MSHC is part of the IQUE bus domain. The register spaces for the MSHC is ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 14.1 Device-specific information The PIM is part of the IPBus domain. The MODRR register within the PIM allows for pin mapping for the 100LQFP package and for the 64 LQFP package. Section ...
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Device-specific information The SMHC is part of the IQUE bus domain. The register spaces for the SMHC is located at addresses $02B0-$02BF. Section 18 Smartmedia RAM (SMRAM) Block Description Consult the SMRAM Block Guide for information about the Smartmedia ...
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... MC9S12UF32 design items: • Operation mode • Clocks • Power • USB connector (CON1) • Background debug connector (CON2) To configure the MC9S12UF32 in normal single-chip mode, the MODC, MODB, and MODA pins should be configured as documented in the device overview chapter of this book. 94 Freescale Semiconductor ...
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... Clocking Notes For proper operation of USB and storage interface of the MC9S12UF32, a 12-MHz crystal is required to provide the clock input to the integrated USB PHY. The crystal must connect to the MC9S12UF32 in a Pierce configuration by the XTAL and EXTAL pins as shown. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 22.2 PCB Design Recommendation The PCB must be carefully laid out to ensure proper operations of the voltage regulator as well as the MCU itself. The following rules must be observed: • ...
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... All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations. A.1.2 Power Supply The MC9S12UF32 utilizes several pins to supply power to the I/O ports, the oscillator, USB physical layer interface as well as the digital core. The VDDX, VSSX pair supplies the 3.3V/5V I/O pins of ports and U. ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 A.1.3 Pins There are six groups of functional pins. A.1.3.1 3.3V/5.0V I/O pins on VDDX Those I/O pins have a nominal level of 3.3V or 5.0V depending on the voltage supplied by ...
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A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 A device will be defined as a failure if after exposure to ESD pulses, the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the ...
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NOTE: Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Rating Regulator Supply Voltage VDDX Supply Voltage VDD3X Supply Voltage ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 is the current shown in Table A-8 and not the overall current flowing into VDDR, which I DDR additionally contains the current flowing into the external loads with output high. Which is ...
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A.1.9 I/O Characteristics This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 103 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P Input High Voltage Input High Voltage 1 P Input Low Voltage Input ...
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NOTES refers to 5V supply voltage (VDDR, VDDX, VDD3X). DD5 2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each the temperature range from 50 C ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P Input High Voltage Input High Voltage 1 P Input Low Voltage Input ...
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Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each the temperature range from 125 C. 3. Refer to Section A.1.4 Current Injection, for more ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise ...
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A.2 NVM, Flash NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for Flash. A.2.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency f ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 The setup time can be ignored for this operation. A.2.1.4 Mass Erase Erasing a NVM block takes: The setup time can be ignored for this operation. A.2.1.5 Blank Check The time it ...
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A.2.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 112 Freescale Semiconductor ...
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A.3 Voltage Regulator The on-chip voltage regulator is intended to supply the internal logic, oscillator circuits, and the USB PHY. No external DC load is allowed. Table A-11 Voltage Regulator Recommended Load Resistances/Capacitances Rating Load Capacitance between VDDA and VSSA1 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 114 Freescale Semiconductor ...
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A.4 Reset, Oscillator and PHY This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and USB Physical Layer (PHY). A.4.1 Startup Table A-12 summarizes several startup characteristics explained in this section. Detailed description of the startup ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 A.4.1.5 Wait Recovery The oscillator is not stopped in Wait. The controller can be woken up by internal or external interrupts. After t the CPU starts fetching the interrupt vector. wrs 116 ...
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A.4.2 Oscillator The device features an internal Pierce oscillator. The XCLKS signal of the OSC module is tied internally that the Pierce oscillator/external clock mode is always selected. Pierce oscillator/external clock mode allows the input of a square wave. . ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 118 Freescale Semiconductor ...
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A.5 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-1 with the actual timing values shown on table Table A-15. All major bus signals are included in the diagram. While both a data write ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table A-15 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 1 P Frequency of operation (E-clock Cycle time 3 D Pulse ...
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Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 121 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 122 Freescale Semiconductor ...
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... Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12UF32 packages. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 123 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 B.2 100-pin LQFP Package Figure B-1 100-pin LQFP mechanical dimensions (case no. 983) 124 Freescale Semiconductor ...
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B.3 64-pin LQFP Package 4X 0.2 H A– VIEW D1/2 D SEATING C PLANE X X= e/2 AB 60X VIEW Y Figure ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 126 Freescale Semiconductor ...
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System on a Chip Guide End Sheet Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 127 ...
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System on a Chip Guide — 9S12UF32DGV1/D V01.05 128 FINAL PAGE OF 128 PAGES Freescale Semiconductor ...