mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet - Page 65

• Manufacturer Part Number: mc9s12uf32
• Description: System Chip Guide V01.05
• Manufacturer: Freescale Semiconductor, Inc

System on a Chip Guide — 9S12UF32DGV1/D V01.05
Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the
ATA5HC Block Guide for information about pin configurations.
2.4.47 PS4 / CFIORD / ATAIORD — Port S I/O Pin 4
PS4 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PS4 becomes the compact flash I/O read pin, CFIORD. When the CFHC is not enabled, it can be
configured as the ATA I/O read pin, ATAIORD, when the ATA5 host controller (ATA5HC) is enabled.
While in reset and immediately out of reset the PS4 pin is configured as a high impedance input pin.
Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the
ATA5HC Block Guide for information about pin configurations.
2.4.48 PS3 / CFCE2 / ATACS1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PS3 becomes the compact flash chip enable 2 pin, CFCE2. When the CFHC is not enabled, it can be
configured as the ATA chip select 1 pin, ATACS1, when the ATA5 host controller (ATA5HC) is enabled.
While in reset and immediately out of reset the PS3 pin is configured as a high impedance input pin.
Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the
ATA5HC Block Guide for information about pin configurations.
2.4.49 PS2 / CFIOIS16 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PS2 becomes the compact flash I/O select 16-bit pin, CFIOIS16. While in reset and immediately out of
reset the PS2 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM)
PIM_9UF32 Block Guide and the CFHC Block Guide for information about pin configurations.
2.4.50 PS1 / CFOE — Port S I/O Pin 1
PS1 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PS1 becomes the compact flash output enable pin, CFOE. While in reset and immediately out of reset the
PS2 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM)
PIM_9UF32 Block Guide and the CFHC Block Guide for information about pin configurations.
2.4.51 PS0 / CFCE1 / ATACS0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PS0 becomes the compact flash chip enable 1 pin, CFCE1. When the CFHC is not enabled, it can be
configured as the ATA chip select 0 pin, ATACS0, when the ATA5 host controller (ATA5HC) is enabled.
While in reset and immediately out of reset the PS0 pin is configured as a high impedance input pin.
Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the
ATA5HC Block Guide for information about pin configurations.
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