mc9rs08ka2 Freescale Semiconductor, Inc, mc9rs08ka2 Datasheet - Page 77

• Manufacturer Part Number: mc9rs08ka2
• Description: Rs08 Microcontrollers 8-bit Microcontroller Family
• Manufacturer: Freescale Semiconductor, Inc

9.4.2
9.4.3
Freescale Semiconductor
Field
BDIV
Field
TRIM
7:6
7:0
LP
3
Reset:
Reset:
POR:
W
R
W
R
ICS Control Register 2 (ICSC2)
ICS Trim Register (ICSTRM)
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bit. This
controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
Low Power Select — Controls whether the FLL is disabled in FLL bypassed modes.
1 FLL is disabled in bypass modes
0 FLL is not disabled in bypass mode
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
0
7
U
7
1
BDIV
= Unimplemented
1
6
U
0
6
Figure 9-4. ICS Control Register 2 (ICSC2)
Figure 9-5. ICS Trim Register (ICSTRM)
Table 9-4. ICSTRM Field Descriptions
MC9RS08KA2 Series Data Sheet, Rev. 3
Table 9-3. ICSC2 Field Descriptions
5
0
0
U
0
5
0
0
4
U
0
4
Description
Description
TRIM
LP
0
3
U
0
3
Chapter 9 Internal Clock Source (RS08ICSV1)
0
0
2
U
0
2
0
0
1
U
0
1
U
0
0
0
0
0
77