m38039g6hsp Renesas Electronics Corporation., m38039g6hsp Datasheet
m38039g6hsp
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m38039g6hsp Summary of contents
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Group (Spec.H QzROM version) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3803 group (Spec.H QzROM version) is the 8-bit microcomputer based on the 740 family core technology. The 3803 group (Spec.H QzROM version) is designed for household products, office automation ...
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... ROM size for User M38039G4H-XXXHP M38039G4H-XXXKP M38039G6H-XXXHP M38039G6H-XXXKP M38039G8H-XXXHP M38039G8H-XXXKP M38039GCH-XXXHP M38039GCH-XXXKP M38039G4HSP M38039G4HHP M38039G4HKP M38039G6HSP M38039G6HHP M38039G6HKP M38039G8HSP M38039G8HHP M38039G8HKP M38039GCHSP M38039GCHHP M38039GCHKP NOTES: 1. This means a shipment of which User ROM has been programmed. 2. The user ROM area of a blank product is blank. ...
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Group (Spec.H QzROM version) PIN CONFIGURATION (TOP VIEW RDY3 CLK3 / /DA 0 ...
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... PIN CONFIGURATION (TOP VIEW) Fig 2. 3803 group (Spec.H QzROM version) pin configuration (PRDP0064BA-A) Table 3 List of package (Spec.H QzROM version) (PRDP0064BA-A) Package Product name M38039G4HSP M38039G6HSP PRDP0064BA-A M38039G8HSP M38039GCHSP NOTES: 1. The user ROM area of a blank product is blank. Rev.1.10 Nov 14, 2005 Page ...
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Group (Spec.H QzROM version) Fig 3. Functional block diagram Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. ...
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Group (Spec.H QzROM version) PIN DESCRIPTION Table 4 Pin description Pin Name Power source CC SS CNV CNV input Reference REF voltage AV Analog power SS source RESET Reset input X Clock input ...
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Group (Spec.H QzROM version) PART NUMBERING Product name M3803 9 G Fig 4. Part numbering Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 C H − XXX SP Package type SP : PRDP0064BA PLQP0064KB ...
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Group (Spec.H QzROM version) GROUP EXPANSION Renesas Technology expands the 3803 group (Spec.H QzROM version) as follows. Memory Type Support for QzROM version. Memory Expansion Plan ROM size (bytes) 48K 32K 24K 16K 640 Notes 1: Products under development: ...
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Group (Spec.H QzROM version) GROUP DESCRIPTION The QzROM version of 3803 group (Spec.H) is under development. The mask ROM version and the flash memory version are mass production. Currently support products are listed below. Table 5 Support products (mask ...
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Group (Spec.H QzROM version) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3803 group (Spec.H QzROM version) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family ...
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Group (Spec.H QzROM version) Interrupt request Push Return M(S)←( Address on Stack (S)←(S) − 1 M(S)←( ← − Subroutine Execute RTS (S)←( POP Return Address from ...
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Group (Spec.H QzROM version) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch ...
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Group (Spec.H QzROM version) [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, the internal system clock control bits, etc. The CPU mode register is allocated at address 003B b7 Fig 8. Structure ...
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Group (Spec.H QzROM version) MISRG (1) Bit 0 of address 0010 : Oscillation stabilizing time 16 set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been ...
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Group (Spec.H QzROM version) MEMORY • Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. • RAM The RAM is used for data storage and ...
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Group (Spec.H QzROM version) Port P0 (P0) 0000 16 Port P0 direction register (P0D) 0001 16 Port P1 (P1) 0002 16 Port P1 direction register (P1D) 0003 16 Port P2 (P2) 0004 16 Port P2 direction register (P2D) 0005 ...
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Group (Spec.H QzROM version) I/O PORTS The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be ...
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Group (Spec.H QzROM version) (1) Ports Pull-up control bit Direction register Port latch Data bus A/D converter input (3) Ports Pull-up control bit Direction register Data bus Port latch ...
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Group (Spec.H QzROM version) (9) Port P3 7 Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit S output enable bit RDY3 Direction register Data bus Port latch Serial I/O3 ready output (11) Port P4 1 ...
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Group (Spec.H QzROM version) (15) Port P5 2 Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Port latch Serial I/O2 clock output Serial I/O2 external clock input (17) Ports ...
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Group (Spec.H QzROM version Fig 15. Structure of port pull-up control register (1) Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 Port P0 pull-up control register (PULL0: address 0FF0 ) 16 P0 pull-up control ...
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Group (Spec.H QzROM version Fig 16. Structure of port pull-up control register (2) Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 Port P2 pull-up control register (PULL2: address 0FF2 ) 16 P2 pull-up control ...
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Group (Spec.H QzROM version Fig 17. Structure of port pull-up control register (3) Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 Port P4 pull-up control register (PULL4: address 0FF4 ) 16 P4 pull-up control ...
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Group (Spec.H QzROM version Fig 18. Structure of port pull-up control register (4) Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 Port P6 pull-up control register (PULL6: address 0FF6 ) 16 P6 pull-up control bit 0 ...
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Group (Spec.H QzROM version) INTERRUPTS The 3803 group (Spec.H QzROM version)’s interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software. • Interrupt Control Each interrupt is controlled ...
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Group (Spec.H QzROM version) Table 9 Interrupt vector addresses and priority Addresses Interrupt Source Priority High (2) 1 FFFD Reset INT 2 FFFB 0 Timer Z INT 3 FFF9 1 Serial I/O1 reception 4 FFF7 Serial I/O1 5 FFF5 ...
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Group (Spec.H QzROM version) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Fig 19. Interrupt control Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 PRELIMINARY Notice: This is not a final specification. Some parametric limits are ...
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Group (Spec.H QzROM version Interrupt edge selection register (INTEDGE : address 003A INT interrupt edge selection bit 0 INT interrupt edge selection bit 1 Not used (returns “0” when read) INT interrupt edge selection bit 2 INT ...
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Group (Spec.H QzROM version) TIMERS • 8-bit Timers The 3803 group (Spec.H QzROM version) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and ...
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Group (Spec.H QzROM version) (4) Pulse Width Measurement Mode • Mode selection This mode can be selected by setting “11” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits ...
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Group (Spec.H QzROM version “00” (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) “11” Divider Count source selection bit “10” X CIN Main clock division ratio selection bits f(X ) CIN CNTR active 0 edge ...
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Group (Spec.H QzROM version) b7 Fig 22. Structure of timer XY mode register Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 b0 Timer XY mode register (TM : address 0023 ) 16 Timer X operating mode bits b1 ...
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Group (Spec.H QzROM version Fig 23. Structure of timer 12, X and timer Y, Z count source selection registers Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 b0 Timer 12, X count source selection register (T12XCSS ...
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Group (Spec.H QzROM version) • 16-bit Timer The timer 16-bit timer. When the timer reaches “0000 ...
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Group (Spec.H QzROM version) (4) Pulse period measurement mode • Mode selection This mode can be selected by setting “010” to the timer Z operating mode bits (bits and setting “0” to the timer/event counter mode ...
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Group (Spec.H QzROM version) (6) Programmable waveform generating mode • Mode selection This mode can be selected by setting “100” to the timer Z operating mode bits (bits and setting “0” to the timer/event counter mode ...
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Group (Spec.H QzROM version) P4 /INT 2 1 Programmable one-shot generating mode Output level latch “001” “100” “101” Timer Z operating mode bits Port P4 latch Port P4 7 direction register Pulse period measurement mode Pulse width measurement mode ...
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Group (Spec.H QzROM version Note: When selecting the modes except the timer/event counter mode, set “0” to this bit. Fig 25. Structure of timer Z mode register Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 Timer ...
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Group (Spec.H QzROM version) FFFF 16 TL 0000 16 Fig 26. Timing chart of timer/event counter mode FFFF TL 0000 Waveform output from CNTR pin 2 Fig 27. Timing chart of pulse output mode Rev.1.10 Nov 14, 2005 Page ...
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Group (Spec.H QzROM version) 0000 FFFF 16 Signal input from CNTR pin 2 Fig 28. Timing chart of pulse period measurement mode (Measuring term between two rising edges) 0000 FFFF 16 ...
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Group (Spec.H QzROM version) FFFF 0000 Signal output from CNTR pin 2 Fig 30. Timing chart of programmable waveform generating mode FFFF Signal input from INT pin 1 Signal output from CNTR pin 2 Fig 31. Timing chart of ...
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Group (Spec.H QzROM version) SERIAL INTERFACE • Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation ...
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Group (Spec.H QzROM version) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data ...
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Group (Spec.H QzROM version) [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 0018 16 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive ...
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Group (Spec.H QzROM version) Serial I/O1 status register b7 b0 (SIO1STS : address 0019 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion ...
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Group (Spec.H QzROM version) <Notes concerning serial I/O1> 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation • Note Clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O and ...
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Group (Spec.H QzROM version output of reception side RDY1 • Note When signals are output from the S side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable ...
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Group (Spec.H QzROM version) • Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock ...
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Group (Spec.H QzROM version) Transfer clock (Note 1) Serial I/O2 register write signal Serial I/O2 output S OUT2 Serial I/O2 input S IN2 Receive enable signal S RDY2 Notes1: When the internal clock is selected as the transfer clock, ...
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Group (Spec.H QzROM version) • Serial I/O3 Serial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O3. A dedicated timer is also provided for baud rate generation ...
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Group (Spec.H QzROM version) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit (b6) of the serial I/O3 control register to “0”. Eight serial data ...
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Group (Spec.H QzROM version) [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 0030 16 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive ...
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Group (Spec.H QzROM version) Serial I/O3 status register b7 b0 (SIO3STS : address 0031 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion ...
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Group (Spec.H QzROM version) <Notes concerning serial I/O3> 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation • Note Clear the serial I/O3 enable bit and the transmit enable bit to “0” (serial I/O and ...
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Group (Spec.H QzROM version output of reception side RDY3 • Note When signals are output from the S RDY3 side by using an external clock in the clock synchronous serial I/O mode, set all of the receive ...
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Group (Spec.H QzROM version) PULSE WIDTH MODULATION (PWM) The 3803 group (Spec.H QzROM version) has PWM functions with an 8-bit resolution, based on a signal that is the clock input X or that clock input divided ...
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Group (Spec.H QzROM version) b7 Fig 47. Structure of PWM control register PWM output PWM register write signal PWM prescaler write signal When the contents of the PWM register or PWM prescaler have changed, the PWM output will change ...
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Group (Spec.H QzROM version) A/D CONVERTER [AD Conversion Register 1, 2 (AD1, AD2)] 0035 0038 16 The AD conversion register is a read-only register that stores the result of an A/D conversion. When reading this register during an A/D ...
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Group (Spec.H QzROM version) b7 AD/DA control register (Address 0034 ) Comparator /AN ...
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Group (Spec.H QzROM version) D/A CONVERTER The 3803 group (Spec.H QzROM version) has two internal D/A converters (DA and DA ) with 8-bit resolution The D/A conversion is performed by setting the value in each DA conversion ...
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Group (Spec.H QzROM version) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of ...
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Group (Spec.H QzROM version) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more Then the RESET pin is IN returned to an “H” level (the ...
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Group (Spec.H QzROM version) (1) Port P0 (P0) (2) Port P0 direction register (P0D) (3) Port P1 (P1) (4) Port P1 direction register (P1D) (5) Port P2 (P2) (6) Port P2 direction register (P2D) (7) Port P3 (P3) (8) ...
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Group (Spec.H QzROM version) CLOCK GENERATING CIRCUIT The 3803 group (Spec.H QzROM version) has two built-in oscillation circuits: main clock OUT sub clock X -X oscillation circuit. An oscillation circuit CIN COUT can be formed by ...
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Group (Spec.H QzROM version CIN COUT CIN COUT Notes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use ...
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Group (Spec.H QzROM version COUT CIN “0” “1” Port X C switch bit OUT Main clock division ratio selection bits (Note 1) (Note 4) Low-speed mode High-speed or middle-speed mode Main clock stop bit ...
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Group (Spec.H QzROM version) Reset Middle-speed mode CM (f(φ MHz) “1”←→”0” MHz oscillating (32 kHz stopped) 4 Middle-speed mode CM (f(φ MHz) “1”←→”0” ...
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Group (Spec.H QzROM version) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which ...
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Group (Spec.H QzROM version) NOTES ON USAGE Termination of Unused Pins. Be sure to perform the termination of unused pins. Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies ...
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Group (Spec.H QzROM version) ELECTRICAL CHARACTERISTICS Absolute maximum ratings Table 10 Absolute maximum ratings Symbol Parameter V Power source voltages CC V Input voltage Input voltage P3 ...
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Group (Spec.H QzROM version) Recommended operating conditions Table 11 Recommended operating conditions ( 1 Symbol Parameter V Power source When start oscillating CC (1) voltage High-speed mode f( φ ...
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Group (Spec.H QzROM version) Table 12 Recommended operating conditions ( 1 Symbol Σ I “H” total peak output current OH(peak) Σ I “H” total peak output current OH(peak) Σ I “L” ...
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Group (Spec.H QzROM version) Electrical characteristics Table 13 Electrical characteristics ( 1 Symbol Parameter V (1) “H” output voltage ...
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Group (Spec.H QzROM version) Table 14 Electrical characteristics ( 1 – °C, f(X CC Output transistors “off”, AD converter not operated) Symbol Parameter I Power source High-speed CC current mode ...
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Group (Spec.H QzROM version) A/D converter characteristics Table 15 A/D converter recommended operating conditions (V = 2 Symbol Parameter V Power source voltage CC (When A/D converter is used) V Analog convert reference ...
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Group (Spec.H QzROM version) Timing requirements and switching characteristics Table 18 Timing requirements ( 2 Symbol t (RESET) Reset input “L” pulse width Main clock X C ...
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Group (Spec.H QzROM version) Table 19 Timing requirements ( 2 Symbol Serial I/O1, serial I/O3 C CLK1 clock input cycle time C CLK3 t (S ...
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Group (Spec.H QzROM version) Table 20 Switching characteristics ( 2 Symbol Parameter Serial I/O1, serial I/O3 WH CLK1 clock output “H” pulse WH CLK3 width ...
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Group (Spec.H QzROM version) Table 21 Switching characteristics ( 2 Symbol Parameter Serial I/O2 f CLK2 fall time of clock output t (CMOS) CMOS r (1) rise time ...
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Group (Spec.H QzROM version) Measurement output pin Fig 64. Circuit for measuring output switching characteristics (1) Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 Measurement output pin 100pF CMOS output Fig 65. Circuit for measuring output switching characteristics ...
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Group (Spec.H QzROM version) Single-chip mode timing diagram CNTR , CNTR 0 1 CNTR 2 INT , INT , INT INT , INT 00 40 INT , INT 01 41 RESET CIN S ...
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Group (Spec.H QzROM version) PACKAGE OUTLINE JEITA Package Code RENESAS Code P-SDIP64-17x56.4-1.78 PRDP0064BA SEATING PLANE e JEITA Package Code RENESAS Code P-LQFP64-10x10-0.50 PLQP0064KB Index mark ...
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Group (Spec.H QzROM version) JEITA Package Code RENESAS Code P-LQFP64-14x14-0.80 PLQP0064GA Index mark y e Rev.1.10 Nov 14, 2005 Page REJ03B0166-0110 Previous Code MASS[Typ.] 64P6U-A 0.7g ...
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Group (Spec.H QzROM version) APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular essential to initialize the T and ...
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Group (Spec.H QzROM version) NOTES ON PERIPHERAL FUNCTIONS Notes on Input and Output Ports 1. Notes in standby state *1 In standby state for low-power dissipation, do not make input levels of an I/O port “undefined”. Even when an ...
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Group (Spec.H QzROM version) Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence ...
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Group (Spec.H QzROM version) Notes on 8-bit Timer (timer • value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). • When switching the count ...
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Group (Spec.H QzROM version) Notes on Serial Interface 1. Notes when selecting clock synchronous serial I/O (1) Stop of transmission operation As for serial I/ that can be used as either a clock synchronous or ...
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Group (Spec.H QzROM version) Notes on PWM The PWM starts from “H” level after the PWM enable bit is set to enable and “L” level is temporarily output from the PWM pin. The length of this “L” level output ...
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Group (Spec.H QzROM version) Notes on Restarting Oscillation • Restarting oscillation Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has been released by an external interrupt source, the fixed values of Timer ...
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Group (Spec.H QzROM version) QzROM Version Connect the CNV /V pin the shortest possible to the GND SS PP pattern which is supplied to the V pin of the microcomputer addition connecting an approximately 5 kΩ resistor ...
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REVISION HISTORY REVISION HISTORY Rev. Date Page − 1.00 Sep. 30, 2005 1.10 Nov. 14, 2005 82-83 84-91 3803 Group (Spec.H QzROM version) Data Sheet Description First edition issued Fig 14. Port block diagram (3) (18) Port ...