m38039g6hsp Renesas Electronics Corporation., m38039g6hsp Datasheet - Page 84

• Manufacturer Part Number: m38039g6hsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Renesas Electronics Corporation.

3803 Group (Spec.H QzROM version)
Rev.1.10
REJ03B0166-0110
APPENDIX
NOTES ON PROGRAMMING
1. Processor Status Register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because
they have an important effect on calculations.
<Reason>
After a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
Fig 1.
(2) How to reference the processor status register
To reference the contents of the processor status register (PS),
execute the PHP instruction once then read the contents of (S+1).
If necessary, execute the PLP instruction to return the PS to its
original status.
Fig 2.
2. BRK instruction
(1) Interrupt priority level
When the BRK instruction is executed with the following
conditions satisfied, the interrupt execution is started from the
address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
3. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield
proper decimal notation, set the decimal mode flag (D) to “1”
with the SED instruction. After executing the ADC or SBC
instruction, execute another instruction before executing the
SEC, CLC, or CLD instruction.
(2) Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC
or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the
calculation, or is cleared to “0” if a borrow is generated. To
determine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calculation.
Initialization of processor status register
Stack memory contents after PHP instruction
execution
Nov 14, 2005
(S) + 1
(S)
Initializing of flags
Main program
Reset
Stored PS
Page 84 of 91
Fig 3.
4. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
5. Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not
• The execution of these instructions does not change the
6. Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value
• The bit-test instruction (BBC or BBS, etc.) to a direction
• The read-modify-write instructions (ROR, CLB, or SEB, etc.)
Use instructions such as LDM and STA, etc., to set the port
direction registers.
7. Instruction Execution Timing
The instruction execution time can be obtained by multiplying
the frequency of the internal clock
mentioned in the 740 Family Software Manual.
The frequency of the internal clock
high-speed mode, 8 times the X
and the twice the X
8. Reserved Area, Reserved Bit
Do not write any data to the reserved area in the SFR area and the
special page. (Do not change the contents after reset.)
9. CPU Mode Register
Be sure to fix bit 3 of the CPU mode register (address 003B
“1”.
affect the MUL and DIV instruction.
contents of the processor status register.
of a direction register as an index
register
to a direction register.
Execution of decimal calculations
SEC, CLC, or CLD instruction
CIN
ADC or SBC instruction
in low-speed mode.
Set D flag to “1”
NOP instruction
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
IN
φ
cycle in middle-speed mode,
is the twice the X
φ
by the number of cycles
IN
cycle in
16
) to