r5f5631acdlk Renesas Electronics Corporation., r5f5631acdlk Datasheet - Page 13

• Manufacturer Part Number: r5f5631acdlk
• Description: 100-mhz 32-bit Rx Mcu, On-chip Fpu, 165 Dmips, Up To 2-mb Flash Memory, Ethernet Mac, Full-speed Usb 2.0 Host/function/otg Interface Various Communications Interfaces Including Can, 10- & 12-bit A/d Converters, Rtc
• Manufacturer: Renesas Electronics Corporation.

Under development
RX63N Group, RX631 Group
R01DS0098EJ0050 Rev.0.50
May 13, 2011
Table 1.4
Classifications
Bus control
EXDMA controller
Interrupt
Multi-function timer pulse
unit 2
Port output enable 2
16-bit timer pulse unit
Programmable pulse
generator
8-bit timer
Serial communications
interface (SCIc)
Pin Functions (2 / 5)
Preliminary document
Specifications in this document are tentative and subject to change.
Pin Name
WE#
DQM0 to DQM3
CS0# to CS7#
WAIT#
EDREQ0, EDREQ1
EDACK0, EDACK1
NMI
IRQ0 to IRQ15
MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D
MTIOC1A, MTIOC1B
MTIOC2A, MTIOC2B
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
MTIC5U, MTIC5V
MTIC5W
MTCLKA, MTCLKB
MTCLKC, MTCLKD
POE0# to POE3#
POE8#
TIOCA0, TIOCB0
TIOCC0, TIOCD0
TIOCA1, TIOCB1
TIOCA2, TIOCB2
TIOCA3, TIOCB3
TIOCC3, TIOCD3
TIOCA4, TIOCB4
TIOCA5, TIOCB5
TCLKA, TCLKB
TCLKC, TCLKD
PO0 to PO31
TMO0 to TMO3
TMCI0 to TMCI3
TMRI0 to TMRI3
 Asynchronous mode/clock synchronous mode
SCK0 to SCK11
RXD0 to RXD11
TXD0 to TXD11
CTS0# to CTS11#
RTS0# to RTS11#
 Simple I
SSCL0 to SSCL11
SSDA0 to SSDA11
 Simple SPI mode
2
C mode
I/O
Output
Output
Output
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
Input
Output
Output
Input
Input
I/O
Input
Output
Input
Output
I/O
I/O
Description
Output pin for SDRAM write enable signals.
Output pins for SDRAM I/O data mask enable signals.
Select signals for CS area.
Input pins for wait request signals in access to the external
space.
Input pins for external DMA transfer requests.
Output pins for single address transfer acknowledge signals.
Non-maskable interrupt request signal.
Maskable interrupt request signals.
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins.
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins.
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins.
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins.
The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins.
The TGRU5, TGRV5, and TGRW5 input capture input/dead
time compensation input pins.
Input pins for external clock signals.
Input pins for request signals to place the MTU2A large-current
pins in the high impedance state.
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins.
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins.
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins.
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins.
The TGRA4 and TGRB4 input capture input/output compare
output/PWM output pins.
The TGRA5 and TGRB5 input capture input/output compare
output/PWM output pins.
Input pins for external clock signals.
Output pins for the pulse signals.
Output pins for the compare match signals.
Input pins for the external clock signals that drive for the
counters.
Input pins for the counter-reset signals.
Input/output pins for clock signals.
Input pins for data reception.
Output pins for data transmission.
Transfer start control input pins
Transfer start control output pins
Input/output pins for the I
Input/output pins for the I
2
2
C clock
C data
Page 13 of 101
1. Overview