r5f5631acdlk Renesas Electronics Corporation., r5f5631acdlk Datasheet - Page 51

• Manufacturer Part Number: r5f5631acdlk
• Description: 100-mhz 32-bit Rx Mcu, On-chip Fpu, 165 Dmips, Up To 2-mb Flash Memory, Ethernet Mac, Full-speed Usb 2.0 Host/function/otg Interface Various Communications Interfaces Including Can, 10- & 12-bit A/d Converters, Rtc
• Manufacturer: Renesas Electronics Corporation.

Under development
RX63N Group, RX631 Group
R01DS0098EJ0050 Rev.0.50
May 13, 2011
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
(3) Number of Access Cycles to I/O Registers
The number of access cycles to I/O registers is obtained by following equation.*
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. For the number
of access cycles to each I/O register, see Table 4.1, List of I/O Registers (Address Order).
When peripheral functions connected to internal peripheral bus 2 to 6 or registers for the external bus control unit (except
for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK, BCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access states shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided
clock synchronization cycles will be one BCLK at a maximum. Therefore, one BCLK is added to the number of access
cycles shown in Table 4.1.
Note 1.
 Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP
;; Next process
This applies to the number of cycles when the access from the CPU does not conflict with the instruction
fetching to the external memory or bus access from the different bus master (DMACA or DTC).
[R1].L, R1
Preliminary document
Specifications in this document are tentative and subject to change.
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral bus 1 to 6
1
4. I/O Registers
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