sc16c750-04 NXP Semiconductors, sc16c750-04 Datasheet - Page 16

• Manufacturer Part Number: sc16c750-04
• Description: Sc16c750 Universal Asynchronous Receiver/transmitter Uart With 64-byte Fifo
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7. Register descriptions
Table 8:
[1]
[2]
[3]
[4]
9397 750 11623
Product data
A2 A1 A0 Register Default
General Register Set
0
0
0
0
0
0
1
1
1
1
Special Register Set
0
0
Enhanced Register Set
0
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register is accessible only when LCR is set to ‘BF
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
SC16C750 internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
EFR
[3]
[2]
[4]
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
00
Table 8
The assigned bit functions are more fully defined in
[1]
Bit 7
bit 7
bit 7
0
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
DCD
bit 7
bit 7
bit 15
Auto
CTS
details the assigned bit functions for the fifteen SC16C750 internal registers.
Bit 6
bit 6
bit 6
0
RCVR
trigger
(LSB)
FIFOs
enabled
set break set parity even
0
trans.
empty
RI
bit 6
bit 6
bit 14
Auto RTS 0
Rev. 04 — 20 June 2003
Bit 5
bit 5
bit 5
low
power
mode
64-byte
FIFO
enable
64-byte
FIFO
enable
reserved loop back OUT2,
trans.
holding
empty
DSR
bit 5
bit 5
bit 13
Hex
’.
Bit 4
bit 4
bit 4
Sleep
mode
reserved
0
parity
break
interrupt
CTS
bit 4
bit 4
bit 12
0
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
INT
enable
framing
error
bit 3
bit 3
bit 11
0
DCD
Section 7.1
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Bit 2
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits word
OUT1
parity
error
bit 2
bit 2
bit 10
0
RI
UART with 64-byte FIFO
SC16C750
through
Bit 1
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
0
DSR
Section
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
0
CTS
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7.11.