sc16c850iet NXP Semiconductors, sc16c850iet Datasheet - Page 31

• Manufacturer Part Number: sc16c850iet
• Description: Sc16c850 2.5 V To 3.3 V Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And 16 Mode Or 68 Mode Parallel Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C850_1
Product data sheet
7.10 Scratchpad Register (SPR)
7.11 Divisor Latch (DLL and DLM)
7.12 Transmit FIFO Level Count (TXLVLCNT)
7.13 Receive FIFO Level Count (RXLVLCNT)
7.9 Extra Feature Control Register (EFCR)
This is a write-only register, and it allows the software access to these registers: ‘first extra
feature register set’, ‘second extra feature register set’, Transmit FIFO Level Counter
(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).
Table 22.
Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can
only be accessed if EFCR[2:1] are zeroes.
The SC16C850 provides a temporary data register to store 8 bits of user information.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM, stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
This register is a read-only register. It reports the fill level of the receive FIFO (the number
of characters in the RX FIFO).
Bit
7:3
2:1
0
Symbol
EFCR[7:3]
EFCR[2:1]
EFCR[0]
Extra Feature Control Register bits description
2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 01 — 10 January 2008
Description
reserved
Enable Extra Feature Control bits
Enable TXLVLCNT and RXLVLCNT access
00 = General register set is accessible
01 = First extra feature register set is accessible
10 = Second extra feature register set is accessible
11 = reserved
0 = TXLVLCNT and RXLVLCNT are disabled
1 = TXLVLCNT and RXLVLCNT are enabled and can be read.
SC16C850
© NXP B.V. 2008. All rights reserved.
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