sc16c2550-03 NXP Semiconductors, sc16c2550-03 Datasheet
sc16c2550-03
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sc16c2550-03 Summary of contents
Page 1
... An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2550 operates 3.3 V and 2.5 V and the Industrial temperature range, and is available in plastic PLCC44, LQFP48 and DIP40 packages. 2. Features 2 channel UART ...
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... Even-, Odd-, or No-Parity formats 1 1 2-stop bit 2 Baud generation (DC to 1.5 Mbit/s) Loop-back controls for communications link fault isolation Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder Version SOT129-1 SOT187-2 7 1.4 mm SOT313-2 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... REGISTER CSA SELECT CSB LOGIC INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB LOGIC Fig 1. SC16C2550 block diagram. 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA TRANSMIT FIFO REGISTER RECEIVE FIFO REGISTER CLOCK AND ...
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... CSA 14 27 CSB 15 26 XTAL1 16 25 XTAL2 17 24 IOW 18 23 CDB 19 22 GND 20 21 002aaa105 Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder V CC RIA CDA DSRA CTSA RESET DTRB DTRA RTSA OP2A INTA INTB CTSB RTSB RIB DSRB IOR © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Dual UART with 16 bytes of transmit and receive FIFOs and IrDA RXB RXA 11 SC16C2550IA44 TXRDYB 12 13 TXA TXB 14 OP2B 15 16 CSA CSB 17 Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder 39 RESET 38 DTRB 37 DTRA 36 RTSA 35 OP2A 34 RXRDYA 33 INTA 32 INTB 002aaa103 © ...
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... Chip Select A, B (Active-LOW). This function is associated with individual channels, A through B. These pins enable data transfers between the user CPU and the SC16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective CSA, CSB pin. ...
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... I Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load the contents of an internal register defined by address bits A0-A2 onto the SC16C2550 data bus (D0-D7) for access by external CPU. I Write strobe (Active-LOW strobe). A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defi ...
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... TX data is connected to the UART RX input, internally. O Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C2550. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. Rev. 03 — ...
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... The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C2550 is capable of operation Mbits/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460 ...
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... CSA-CSB = 1 CSA = 0 CSB = 0 6.2 Internal registers The SC16C2550 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO ...
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... EFR[7] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C2550 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS input returns to a logic 0, indicating more data may be sent ...
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... In the event that the receive buffer is overfilling and flow control needs to be executed, the SC16C2550 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The SC16C2550 sends the Xoff1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the SC16C2550 will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level ...
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... TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a frequency MHz. To obtain maximum data rate necessary to use full rail swing on the clock input. The SC16C2550 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins ...
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... Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC16C2550 sets the TXRDY (or RXRDY) output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level ...
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... RECEIVE FIFO SHIFT REGISTER REGISTER MODEM CONTROL CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder TXA, TXB MCR[ RXA, RXB RTSA, RTSB CTSA, CTSB DTRA, DTRB DSRA, DSRB LOGIC (OP1A, OP1B) RIA, RIB (OP2A, OP2B) CDA, CDB 002aaa120 © ...
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... Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA details the assigned bit functions for the SC16C2550 internal registers. The Bit 7 Bit 6 Bit 5 ...
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... The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
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... FIFO drops below the trigger level. Logic 0 = Disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition). Logic 1 = Enable the RXRDY (ISR level 2) interrupt. Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Philips Semiconductors 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2550 in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s) ...
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... FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode ‘1’: When the SC16C2550 is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached Receive Time-Out has occurred, the RXRDY pin on PLCC44 and LQFP48 packages will logic 0 ...
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... Interrupt Status Register (ISR) The SC16C2550 provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced ...
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... ISR[7-6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being used in the 16C450 mode. They are set to a logic 1 when the FIFOs are enabled in the SC16C2550 mode. Logic 0 or cleared = default condition. ISR[5-4] INT priority bits 4-3. These bits are enabled when EFR[4] is set to a logic 1 ...
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... LCR[2] stop bit length Word length Stop bit length (bit times LCR[1-0] word length LCR[0] Word length Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Logic 1 = Forces the INT (A-B outputs to the active mode and sets OP2 to a logic 0. MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC16C2550. This bit is instead used in the Loop-back mode only. In the loop-back mode, this bit is used to write the state of the modem RI interface signal. MCR[1] RTS Logic 0 = Force RTS output to a logic 1 (normal default condition) ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2550 and the CPU. Table 18: Bit 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA Line Status Register bits description ...
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... Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C2550 is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register ...
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... Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C2550 provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. ...
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... SC16C554 mode. (Normal default condition.) Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1, all enhanced features of the SC16C2550 are enabled and user settings stored during a reset will be restored. EFR[3-0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition. ...
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... Philips Semiconductors 7.11 SC16C2550 external reset condition Table 22: Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 23: Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB INTA, INTB 8. Limiting values Table 24: In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... OL (databus 1 0.4 OL (other outputs (databus (other outputs 800 A 1. (data bus 400 A 1. (other outputs MHz - 3 Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder 3.3 V 5.0 V Unit Min Max Min Max 0.3 0.6 0.5 0.6 V 2 0.3 0.8 0.5 0.8 V 2 ...
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... Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder 3.3 V 5.0 V Unit Min Max Min Max MHz ...
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... Dual UART with 16 bytes of transmit and receive FIFOs and IrDA t 6h VALID ADDRESS t 13h ACTIVE t 15d t 13w ACTIVE t 16h t 16s DATA t 6h VALID ADDRESS t 7h ACTIVE ACTIVE t 12h t 12d DATA Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder 002aaa109 002aaa110 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Dual UART with 16 bytes of transmit and receive FIFOs and IrDA t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE t 19d ACTIVE Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder CHANGE OF STATE t 18d ACTIVE ACTIVE ACTIVE ACTIVE t 18d CHANGE OF STATE 002aaa111 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 002aaa112 ...
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... Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder NEXT DATA PARITY STOP START BIT BIT BIT 20d ...
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... Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5– DATA BITS (5– Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder NEXT DATA PARITY STOP START BIT BIT BIT 25d ACTIVE DATA READY ...
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... Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder NEXT DATA PARITY STOP START BIT BIT BIT 24d ACTIVE 002aaa116 © ...
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... Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5- ACTIVE TRANSMITTER READY TRANSMITTER NOT READY Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder NEXT DATA START PARITY STOP BIT BIT BIT © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Dual UART with 16 bytes of transmit and receive FIFOs and IrDA DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder PARITY STOP BIT BIT D6 D7 002aaa118 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... 0.53 0.36 52.5 14.1 2.54 0.38 0.23 51.5 13.7 0.021 0.014 2.067 0.56 0.1 0.015 0.009 2.028 0.54 REFERENCES JEDEC JEITA MO-015 SC-511-40 Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder 3.60 15.80 17.42 15.24 0.254 3.05 15.24 15.90 0.14 0.62 0.69 0.6 0.01 0.12 0.60 0.63 EUROPEAN ISSUE DATE ...
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... 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.656 0.656 0.63 0.63 0.695 0.695 0.048 0.05 0.650 0.650 0.59 0.59 0.685 0.685 0.042 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder SOT187 detail X (1) ( max. max. 1.44 0.18 0.18 0.1 2.16 2.16 1 ...
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... 2 scale (1) ( 0.18 7.1 7.1 9.15 9.15 1 0.5 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder SOT313 detail X (1) ( 0.75 0.95 0.95 7 0.2 0.12 0.1 o 0.45 0.55 0.55 0 EUROPEAN ISSUE DATE PROJECTION ...
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... C (SnPb process) or below 245 C (Pb-free process) – for all the BGA and SSOP-T packages 9397 750 11621 Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder ). stg(max) © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Product data Dual UART with 16 bytes of transmit and receive FIFOs and IrDA 2.5 mm thick/large packages. parallel to the transport direction of the printed-circuit board; transport direction of the printed-circuit board. Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... DHVQFN, HBCC, HBGA, not suitable HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS [6] PLCC , SO, SOJ suitable LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, not recommended VSSOP Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder [2] Reflow Dipping [3] suitable suitable [5] suitable suitable [6][7] suitable [8] suitable 10 C measured in the atmosphere of the refl ...
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... Rev. 03 — 19 June 2003 SC16C2550 encoder/decoder Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC16C2550 external reset condition . . . . . . . 29 © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...