mtc20136pq STMicroelectronics, mtc20136pq Datasheet - Page 15

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mtc20136pq

Manufacturer Part Number
mtc20136pq
Description
Adsl Transceiver Controller
Manufacturer
STMicroelectronics
Datasheet

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Figure 5. SDRAM write access (CAS latency = 3; Burst length = 4)
Memory
Following features are provided for memory access (SRAM or FEPROM) :
– 16 bit databus and 20 bit address bus giving 1Mbyte address space per chip select
– control signals : E_nCS[0:1], E_nOE, E_nWE0, E_nWE1
– setup and wait state insertion
– 8, 16 and 32 bit access by MTC20136 to 8 or 16 bit memory according to little endian convention
Figure 6. EBI memory access (32-bit Word R/W to 16 bit memory), maximum speed timing
E_D[15:0]
E_A[19:2]
E_A[1:0]
E_nWEO
E_nWE1
E_nCSi
E_nOE
S_clk
S_nCS
S_nRAS
S_nCAS
S_nWE
S_DQM[1:0]
S_A[11:0]
S_Q[15:0]
00
A1[19:2]
LSB MSB
EAact
10
EArw
00
LSB
A2[19:2]
EApre
MSB
10
MTC20136
EBI
15/25

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